參數(shù)資料
型號(hào)： 935187130557
廠商： NXP SEMICONDUCTORS
元件分類： 畫面疊加
英文描述： PICTURE-IN-PICTURE IC, PQFP100
封裝： PLASTIC, SOT-317-2, QFP-100
文件頁(yè)數(shù)： 27/43頁(yè)
文件大?。?/td> 250K
代理商： 935187130557
February 1995
33
Philips Semiconductors
Preliminary specication
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
Notes
1. Digital clocks are silent and analog bias current is zero.
2. The HUE and SAT DACs are based on a R2R ladder network as describe in the section “HUE and SAT DACs”. The
maximum output sample frequency is determined by the I2C-bus.
3. The input configuration of the ADCs is depicted in Fig.20. The minimum difference AVrefT AVrefB should be larger
than 1.0 V. The reference voltages can be calculated as follows:
;
4. The internal system frequencies are 1728 times the input frequency. For more detailed information about the clock
generation see section “PLLs and clock generation”.
TDclamp
delay burstkey edge to clamping start
0
s
Tclamp
duration of clamping
2.33
s
VclampY
clamping voltage level Y
ADout =0H
Vs
V
VclampU
clamping voltage level U
ADout = 20H
0.5 VT+B
V
VclampV
clamping voltage level V
ADout = 20H
0.5 VT+B
V
Digital-to-analog converter
VrefT
top reference voltage (Y, U and V)
note 3
1.0
1.5
2.0
V
Rinref
input resistance VrefT to VrefB
note 3; 1 DAC
tbf
1.0
tbf
k
Vo(max)
maximum output voltage
VrefB
VrefT
V
RL(min)
minimum load resistance
10
k
CL(max)
maximum load capacitance
50
pF
Res
resolution
7
bit
fs
sample frequency rate
note 4
27
MHz
DNL
differential non-linearity
0.5
+0.5
LSB
INL
integral non-linearity
1.0
+1.0
LSB
α
cs
channel separation
tbf
40
dB
PSRR
power supply rejection ratio
tbf
40
dB
Digital-to-analog converter HUE/SAT
Vo
output voltage
VSS
VDD
V
RL(min)
minimum load resistance
note 2
100
k
CL(max)
maximum load capacitance
50
pF
Res
resolution
6
bit
DNL
differential non-linearity
1.0
+1.0
LSB
INL
integral non-linearity
1.0
+1.0
LSB
PSRR
power supply rejection ratio
note 2
0
dB
PLL and clock generation; note 4
VTOP
TOP-level input voltage
2.5
PVDD
V
VLOW
LOW-level input voltage
0.5
V
Vslice
slicing voltage level below TOP
0.45
1.0
2.0
V
fPLL
input frequency
14750
15734
17250
Hz
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
refT
AV
DD
1.9
5.0
--------
×
V
=
V
refB
AV
DD
0.4
5.0
--------
×
V
=
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