參數(shù)資料
型號： 935045620112
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 52/80頁
文件大?。?/td> 446K
代理商： 935045620112
1997 Dec 15
56
Philips Semiconductors
Product specication
8-bit microcontrollers
P83C524; P80C528; P83C528
21 AC CHARACTERISTICS
21.1
AC Characteristics 16 MHz version
See notes 1, 2 and 3 in Section 21.2; Cl = 100 pF for Port 0, ALE and PSEN; CL = 80 pF for all other outputs unless
otherwise specied.
SYMBOL
PARAMETER
16 MHZ
VARIABLE CLOCK
UNIT
MIN.
MAX.
MIN.
MAX.
External program memory
tLHLL
ALE pulse duration
85
2 tCK40
ns
tAVLL
address set-up time to ALE
8
tCK55
ns
tLLAX
address hold time after ALE
28
tCK35
ns
tLLIV
time from ALE to valid instruction input
150
4 tCK100
ns
tLLPL
time from ALE to control pulse PSEN
23
tCK40
ns
tPLPH
control pulse duration PSEN
143
3 tCK45
ns
tPLIV
time from PSEN to valid instruction input
83
3 tCK105
ns
tPXIX
input instruction hold time after PSEN
0
0
ns
tPXIZ
input instruction oat delay after PSEN
38
tCK25
ns
tAVIV
address to valid instruction input
208
5 tCK105
ns
tPLAZ
address oat time to PSEN
10
10
ns
External data memory
tLHLL
ALE pulse duration
85
2 tCK40
ns
tAVLL
address set-up time to ALE
8
tCK55
ns
tLLAX
address hold time after ALE
28
tCK35
ns
tRLRH
RD pulse duration
275
6 tCK100
ns
tWLWH
WR pulse duration
275
6 tCK100
ns
tRLDV
RD to valid data input
148
5 tCK165
ns
tRHDX
data hold time after RD
0
0
ns
tRHDZ
data oat delay after RD
55
2 tCK70
ns
tLLDZ
time from ALE to valid data input
350
8 tCK150
ns
tAVDV
address to valid data input
398
9 tCK165
ns
tLLWL
time from ALE to RD or WR
138
238
3 tCK50
3 tCK+50
ns
tAVWL
time from address to RD or WR
120
4 tCK130
ns
tWHLH
time from RD or WR HIGH to ALE HIGH
23
103
tCK40
tCK+ 40
ns
tQVWX
data valid to WR transition
3
tCK60
ns
tQVWH
data set-up time before WR
288
7 tCK150
ns
tWHQX
data hold time after WR
13
tCK50
ns
tRLAZ
address oat delay after RD
0
0ns
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