參數(shù)資料
型號： 935044180699
廠商： NXP SEMICONDUCTORS
元件分類： PLL合成/DDS/VCOs
英文描述： PHASE LOCKED LOOP, PDSO16
封裝： 3.90 MM, PLASTIC, SOT-109, SO-16
文件頁數(shù)： 12/40頁
文件大?。?/td> 240K
代理商： 935044180699
1999 Jan 11
2
Philips Semiconductors
Product specication
PLL with bandgap controlled VCO
74HCT9046A
FEATURES
Low power consumption
Centre frequency up to
17 MHz (typ.) at VCC = 5.5 V
Choice of two phase
comparators(1):
– EXCLUSIVE-OR (PC1)
– Edge-triggered JK flip-flop (PC2)
No dead zone of PC2
Charge pump output on PC2,
whose current is set by an external
resistor Rb
Centre frequency tolerance ±10%
Excellent
voltage-controlled-oscillator (VCO)
linearity
Low frequency drift with supply
voltage and temperature variations
On chip bandgap reference
Glitch free operation of VCO, even
at very low frequencies
Inhibit control for ON/OFF keying
and for low standby power
consumption
Operation power supply voltage
range 4.5 to 5.5 V
Zero voltage offset due to op-amp
buffering
Output capability: standard
ICC category: MSI.
APPLICATIONS
FM modulation and demodulation
where a small centre frequency
tolerance is essential
Frequency synthesis and
multiplication where a low jitter is
required (e.g. Video
picture-in-picture)
Frequency discrimination
(1) Rb connected between pin 15 and
ground: PC2 mode, with PCPOUT at
pin 2.
Pin 15 left open or connected to VCC:
PC1 mode with PC1OUT at pin 2.
Tone decoding
Data synchronization and
conditioning
Voltage-to-frequency conversion
Motor-speed control.
GENERAL DESCRIPTION
The 74HCT9046A is a high-speed
Si-gate CMOS device. It is specified
in compliance with
“JEDEC standard
no. 7A”.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 6 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W)
a) PD = CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
b) fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. Applies to the phase comparator section only (inhibit = HIGH). For power
dissipation of the VCO and demodulator sections see Figs 26 to 28.
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
TYP.
UNIT
fc
VCO centre frequency
C1 = 40 pF;
R1 = 3 k
;
VCC = 5 V
16
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation
capacitance per
package
notes 1 and 2
20
pF
EXTENDED
TYPE NUMBER
PACKAGE
PINS
PIN POSITION
MATERIAL
CODE
74HCT9046AN
16
DIL16
plastic
SOT38Z
74HCT9046AD
16
SO16
plastic
SOT109A
相關(guān)PDF資料
PDF描述
935221200118 PHASE LOCKED LOOP, PDSO16
935221200112 PHASE LOCKED LOOP, PDSO16
935044170112 PHASE LOCKED LOOP, PDIP16
935044180112 PHASE LOCKED LOOP, PDSO16
935044180118 PHASE LOCKED LOOP, PDSO16
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