參數(shù)資料
型號(hào)： 935044180112
廠商： NXP SEMICONDUCTORS
元件分類： PLL合成/DDS/VCOs
英文描述： PHASE LOCKED LOOP, PDSO16
封裝： 3.90 MM, PLASTIC, SOT-109, SO-16
文件頁(yè)數(shù)： 37/40頁(yè)
文件大?。?/td> 240K
代理商： 935044180112
1999 Jan 11
6
Philips Semiconductors
Product specication
PLL with bandgap controlled VCO
74HCT9046A
FUNCTIONAL DESCRIPTION
The 74HCT9046A is a
phase-locked-loop circuit that
comprises a linear VCO and two
different phase comparators (PC1
and PC2) with a common signal input
amplifier and a common comparator
input (see Fig.4). The signal input can
be directly coupled to large voltage
signals (CMOS level), or indirectly
coupled (with a series capacitor) to
small voltage signals. A self-bias
input circuit keeps small voltage
signals within the linear region of the
input amplifiers. With a passive
low-pass filter, the '9046A' forms a
second-order loop PLL.
The principle of this
phase-locked-loop is based on the
familiar HCT4046A. However extra
features are built in, allowing very
high performance phase-locked-loop
applications. This is done, at the
expense of PC3, which is skipped in
this HCT9046A. The PC2 is equipped
with a current source output stage
here. Further a bandgap is applied for
all internal references, allowing a
small centre frequency tolerance. The
details are summed up in the next
section called: “Differences with
respect to the familiar HCT4046A”.
If one is familiar with the HCT4046A
already, it will do to read this section
only.
DIFFERENCES WITH RESPECT TO
THE FAMILIAR HCT4046A
A centre frequency tolerance of
maximum
±10%.
The on board bandgap sets the
internal references resulting in a
minimal frequency shift at supply
voltage variations and temperature
variations.
The value of the frequency offset is
determined by an internal
reference voltage of 2.5 V instead
of VCC 0.7 V. In this way the offset
frequency will not shift over the
supply voltage range.
A current switch charge pump
output on PC2 allows a virtually
ideal performance of PC2. The gain
of PC2 is independent of the
voltage across the low-pass filter.
Further a passive low-pass filter in
the loop achieves an active
performance now. The influence of
the parasitic capacitance of the
PC2 output plays no role here,
resulting in a true correspondence
of the output correction pulse and
the phase difference even up to
phase differences as small as a few
nanoseconds.
Because of its linear performance
without dead zone, higher
impedance values for the filter,
hence lower C-values, can now be
chosen. Correct operation will not
be influenced by parasitic
capacitances as in the instance
with voltage source output of the
4046A.
No PC3 on pin 15 but instead a
resistor connected to GND, which
sets the load/unload currents of the
charge pump (PC2).
Extra GND pin at pin 1 to allow an
excellent FM demodulator
performance even at 10 MHz and
higher.
Combined function of pin 2. If
pin 15 is connected to VCC (no bias
resistor Rb) pin 2 has its familiar
function viz. output of PC1. If at
pin 15 a resistor (Rb) is connected
to GND it is assumed that PC2 has
been chosen as phase comparator.
Connection of Rb is sensed by
internal circuitry and this changes
the function of pin 2 into a lock
detect output (PCPOUT) with the
same characteristics as PCPOUT of
pin 1 of the well known
74HCT4046A.
The inhibit function differs. For the
HCT4046A a HIGH level at the
inhibit input (INH) disables the VCO
and demodulator, while a LOW
level turns both on. For the
74HCT9046A a HIGH level on the
inhibit input disables the whole
circuit to minimize standby power
consumption.
VCO
The VCO requires one external
capacitor C1 (between C1A and C1B)
and one external resistor R1
(between R1 and GND) or two
external resistors R1 and R2
(between R1 and GND, and R2 and
GND). Resistor R1 and capacitor C1
determine the frequency range of the
VCO. Resistor R2 enables the VCO
to have a frequency offset if required
(see Fig.5).
The high input impedance of the VCO
simplifies the design of the low-pass
filters by giving the designer a wide
choice of resistor/capacitor ranges. In
order not to load the low-pass filter, a
demodulator output of the VCO input
voltage is provided at pin 10
(DEMOUT). The DEMOUT voltage
equals that of the VCO input. If
DEMOUT is used, a load resistor (Rs)
should be connected from pin 10 to
GND; if unused, DEMOUT should be
left open. The VCO output (VCOOUT)
can be connected directly to the
comparator input (COMPIN), or
connected via a frequency-divider.
The VCO output signal has a duty
factor of 50% (maximum expected
deviation 1%), if the VCO input is held
at a constant DC level. A LOW level at
the inhibit input (INH) enables the
VCO and demodulator, while a HIGH
level turns both off to minimize
standby power consumption.
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