參數(shù)資料
型號(hào)： 935026920518
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44
封裝： PLASTIC, MO-047AC, SOT-187-2, LCC-44
文件頁(yè)數(shù)： 25/34頁(yè)
文件大?。?/td> 313K
代理商： 935026920518
Philips Semiconductors - PIP - SCN2681; Dual asynchronous receiver/transmitter (DUART)
Product Information
SCN2681; Dual
asynchronous
receiver/transmitter
(DUART)
Information as of 2003-04-22
Stay informed
Download datasheet
Block diagram
topGeneral description
The Philips Semiconductors SCN2681 Dual Universal Asynchronous Receiver/Transmitter (DUART) is a single-chip
MOS-LSI communications device that provides two independent full-duplex asynchronous receiver/transmitter channels in
a single package. It interfaces directly with microprocessors and may be used in a polled or interrupt driven system.
The operating mode and data format of each channel can be programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of eighteen fixed baud rates, a 16X clock derived from a programmable
counter/timer, or an external 1X or 16X clock. The baud rate generator and counter/timer can operate directly from a
crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and
transmitter make the DUART particularly attractive for dual-speed channel applications such as clustered terminal systems.
Each receiver is quadruply buffered to minimize the potential of receiver over-run or to reduce interrupt overhead in
interrupt driven systems. In addition, a flow control capability is provided to disable a remote DUART transmitter when the
buffer of the receiving device is full.
Also provided on the SCN2681 are a multipurpose 7-bit input port and a multipurpose 8-bit output port. These can be used
as general purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under
program control.
The SCN2681 is available in three package versions: 40-pin and 28–pin, both 0.6” wide DIPs; a compact 24-pin 0.4” wide
DIP; and a 44-pin PLCC.
topFeatures
q
Dual full-duplex asynchronous receiver/transmitter
q
Quadruple buffered receiver data registers
q
Programmable data format
– 5 to 8 data bits plus parity
– Odd, even, no parity or force parity
– 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
q
Programmable baud rate for each receiver and transmitter selectable from:
– 22 fixed rates: 50 to 115.2k baud
q
16-bit programmable Counter/Timer
– Non-standard rates to 115.2Kb
– One user-defined rate derived from programmable timer/counter
– External 1X or 16X clock
q
Parity, framing, and overrun error detection
q
False start bit detection
file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/SCN2681AC1N40.html (1 of 4) [Apr-29-2003 9:44:40 AM]
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