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參數資料
| 型號： | 935024380129 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | Buffer和線驅動 |
| 英文描述： | TRIPLE LINE TRANSCEIVER, PDSO16 |
| 封裝： | SOL-16 |
| 文件頁數： | 2/5頁 |
| 文件大?。?/td> | 50K |
| 代理商： | 935024380129 |
Philips Semiconductors Linear Products
Product specification
MC145406
EIA-232-D/V.28 driver/receiver
August 31, 1994
468
BLOCK DIAGRAM
RECEIVER
DO
DI
1.4V
LEVEL
SHIFT
DRIVER
HYSTERESIS
300
15k
5.4k
RX
TX
VCC
VSS
VCC
VDD
VSS
VCC
1.0V
1.8V
+
–
+
–
PIN #
SYMBOL
PIN DESCRIPTION
1
VDD
Positive power supply. The most positive power supply pin, which is typically 5 to 12 volts.
8
VSS
Negative power supply. The most negative power supply pin, which is typically -5 to -12 volts.
16
VCC
Digital power supply. The digital supply pin, which is connected to the logic power supply (maximum +5.5V).
9
GND
Ground. Ground return pin is typically connected to the signal ground pin of the EIA-232-D connector (Pin 7)
as well as to the logic power supply ground.
2, 4, 6
RX1, RX2, RX3
Receive Data Input. These are the EIA-232-D receive signal inputs whose voltages can range from +25 to
-25V. A voltage between +3 and +25 is decoded as a space and causes the corresponding DO pin to swing
to ground (0V); a voltage between -3 and -25V is decoded as a mark and causes the DO pin to swing up to VCC.
The actual turn-on input switchpoint is typically biased at 1.8V above ground, and includes 800mV of hysteresis
for noise rejection. The nominal input impedance is 5k
. An open or grounded input pin is interpreted as a mark,
forcing the DO pin to VCC.
11, 13, 15
DO1, DO2, DO3
Data Output. These are the receiver digital output pins, which swing from VCC to GND. A space on the RX
pin causes DO to produce a logic zero; a mark produces a logic one. Each output pin is capable of driving one
LSTTL input load.
10, 12, 14
DI1, DI2, DI3
Data Input. These are the high-impedance digital input pins to the drivers. TTL compatibility is accomplished
by biasing the input switchpoint at 1.4V above ground. However, 5V CMOS compatibility is maintained as well.
Input voltage levels on these pins must be between VCC and GND.
3, 5, 7
TX1, TX2, TX3
Transmit Data Output. These are the EIA-232-D transmit signal output pins, which swing toward VDD and VSS.
A logic one at a DI input causes the corresponding TX output to swing toward VSS. A logic zero causes the
output to swing toward VDD (the output voltages will be slightly less than VDD or VSS depending upon the output
load). Output slew rates are limited to a maximum of 30V/
s. When the MC145406 is off (VDD = VSS = VCC
= GND), the minimum output impedance is 300
.
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