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參數(shù)資料
| 型號(hào)： | 935008220602 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | F/FAST SERIES, OCTAL 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | 7.50 MM, PLASTIC, MS-013, SOT-137-1, SO-24 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 159K |
| 代理商： | 935008220602 |
Philips Semiconductors
Product data
74F646A/74F648A
Transceivers/registers
74F646A:
Octal transceiver/register, non-inverting (3-State)
74F648A:
Octal transceiver/register, inverting (3-State)
2
2003 Feb 04
FEATURES
Combines 74F245 and two 74F374 type functions in one chip
High impedance base inputs for reduced loading (70 A in HIGH
and LOW states)
Independent registers for A and B buses
Multiplexed real-time and stored data
Choice of non-inverting and inverting data paths
Controlled ramp outputs for 74F646A/74F648A
3-state outputs
300 mil wide 24-pin slim DIP package
DESCRIPTION
The 74F646A and 74F648A transceivers/registers consist of bus
transceiver circuits with 3-state outputs, D-type flip-flops, and control
circuitry arranged for multiplexed transmission of data directly from
the input bus or the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes HIGH.
Output enable (OE) and DIR pins are provided to control the
transceiver function. In the transceiver mode, data present at the
high impedance port may be stored in either the A or B register or
both.
The select pins (SAB, SBA) determine whether data is stored or
transferred through the device in real-time. The DIR determines
which bus will receive data when the OE is active LOW. In the
isolation mode (OE = HIGH), data from bus A may be stored in the
B register and/or data from bus B may be stored in the A register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, A or B may be driven at a time.
TYPE
TYPICAL fmax
TYPICAL SUPPLY CURRENT (TOTAL)
74F646A, 74F648A
185 MHz
105 mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
PKG DWG #
VCC = 5 V ±10%, Tamb = 0 °C to +70 °C
24-pin plastic slim DIP (300 mil)
N74F646AN, N74F648AN
SOT222-1
24-pin plastic SOL
N74F646AD, N74F648AD
SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH / LOW
A0-A7, B0-B7
A and B inputs
3.5 / 0.116
70
A / 70 A
CPAB
A-to-B clock input
1.0 / 0.033
20
A / 20 A
CPBA
B-to-A clock input
1.0 / 0.033
20
A / 20 A
SAB
A-to-B select input
1.0 / 0.033
20
A / 20 A
SBA
B-to-A select input
1.0 / 0.033
20
A / 20 A
DIR
Data flow directional control enable input
1.0 / 0.033
20
A / 20 A
OE
Output enable input
1.0 / 0.033
20
A / 20 A
A0 - A7, B0 - B7
A, B outputs for N74F646A/N74F648A
750 / 80
15 mA / 48 mA
NOTE: One (1.0) FAST unit load is defined as: 20
A in the HIGH state and 0.6 mA in the LOW state.
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