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參數(shù)資料
| 型號： | 935006010112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LCD CLOCK, PDSO28 |
| 封裝： | 7.50 MM, PLASTIC, SOT-136-1, MS-013AE, SOP-28 |
| 文件頁數(shù)： | 2/22頁 |
| 文件大?。?/td> | 153K |
| 代理商： | 935006010112 |
1997 Apr 16
10
Philips Semiconductors
Product specication
4-digit duplex LCD car clock
PCF1178C
CHARACTERISTICS
VDD =3to6V; VSS =0V; Tamb = 40 to +85 °C; crystal: f = 4.194304 MHz; Rs =50 ; CL = 12 pF; maximum
frequency tolerance =
±30 × 106; unless otherwise specied.
Note
1. A suitable resistor (R) must be selected (example):
a) VDD = 5 V; R max. (12 V 5 V)/700 A=10k.
b) VDD = 5 V; R typ. (12 V 5 V)/900 A = 7.8 k (more reserve).
c) IDD must not exceed 3 mA.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
supply voltage
voltage regulator programmed
to 4.5 V at Tamb =25 °C
3
6V
V
DD
supply voltage variation
S1 or S2 closed
50
mV
TC
supply voltage variation due
to temperature
0.35
%/K
VDD = 4.5 V
16
mV/K
IDD
supply current
note 1
700
950
A
CEXT
capacitance
external capacitor
47
F
Oscillator
tosc
start time
200
ms
f/f
frequency deviation
nominal n = 0
0
60
× 106
110
× 106
f/f
frequency stability
VDD = 100 mV
1
× 106
Rfb
feedback resistance
300
1000
3000
k
Ci
input capacitance
16
pF
Co
output capacitance
27
pF
Inputs
RO
pull-up resistance
S1, S2, TS, SEL and DATA
45
90
180
k
RO
pull-up/pull-down resistance
MODE
100
300
1000
k
IIL
leakage current
ENABLE, FLASH
2
A
td
debounce time
S1 and S2 only
30
65
100
ms
VPP programming voltage
IO2
output current
VPP =VDD 5V
70
700
A
during programming
500
A
Backplane (high and low levels)
RBP
output resistance
±100 A
3k
Segment
RSEG
output resistance
±100 A
5k
LCD
Voffset(DC)
DC offset voltage
200 k
/1 nF
50
mV
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