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參數(shù)資料
| 型號(hào)： | 933897000623 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, MS-012AC, SOT-109-1, SO-16 |
| 文件頁(yè)數(shù)： | 7/14頁(yè) |
| 文件大小： | 104K |
| 代理商： | 933897000623 |
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Philips Semiconductors
Product specification
74F191
Up/Down binary counter with reset and ripple clock
2
1995 Jul 17
853–0352 15459
FEATURES
High speed –125MHz typical f
MAX
Synchronous, reversible counting
4-Bit binary
Asynchronous parallel load capability
Cascadable without external logic
Single up/down control input
DESCRIPTION
The 74F191 is a 4-bit binary counter. It contains four edge-triggered
master/slave flip-flops with internal gating and steering logic to
provide asynchronous preset and synchronous count-up and
count-down operations.
Asynchronous parallel load capability permits the counter to be
preset to any desired number. Information present on the parallel
data inputs (D0 - D3) is loaded into the counter and appears on the
outputs when the Parallel Load (PL) input is Low. This operation
overrides the counting function. Counting is inhibited by a High level
on the count enable (CE) input. When CE is Low, internal state
changes are initiated. Overflow/underflow indications are provided
by two types of outputs, the Terminal Count (TC) and Ripple Clock
(RC).
The TC output is normally Low and goes High when: 1) the count
reaches zero in the countdown mode or 2) reaches “15” in the count
up mode. The TC output will remain High until a state change
occurs, either by counting or presetting, or until U/D is changed. TC
output should not be used as a clock signal because it is subject to
decoding spikes. The TC signal is used internally to enable the RC
output. When TC is High and CE is Low, the RC follows the clock
pulse. The RC output essentially duplicates the Low clock pulse
width, although delayed in time by two gate delays.
PIN CONFIGURATION
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CE
Q0
D0
D1
Q1
D2
Q2
GND
CP
Q3
D3
VCC
U/D
RC
TC
PL
SF00729
TYPE
TYPICAL fMAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F191
125MHz
40mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
PKG DWG #
16-pin plastic DIP
N74F191N
SOT38-4
16-pin plastic SO
N74F191D
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 - D3
Data inputs
1.0/1.0
20
A/0.6mA
CE
Count enable input (active Low)
1.0/3.0
20
A/1.8mA
CP
Clock pulse input (active rising edge)
1.0/1.0
20
A/0.6mA
PL
Asynchronous parallel load control input (active Low)
1.0/1.0
20
A/0.6mA
U/D
Up/down count control input
1.0/1.0
20
A/0.6mA
Q0 - Q3
Flip-flop outputs
50/33
1.0mA/20mA
RC
Ripple clock output (active low)
50/33
1.0mA/20mA
TC
Terminal count output
50/33
1.0mA/20mA
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20
A in the High state and 0.6mA in the Low state.
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