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參數(shù)資料
| 型號(hào)： | 933893120623 |
| 廠(chǎng)商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 鎖存器 |
| 英文描述： | F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, MS-012AC, SOT-109-1, SO-16 |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大?。?/td> | 88K |
| 代理商： | 933893120623 |
Philips Semiconductors
Product specification
74F173
Quad D-type flip–flop (3-State)
August 31, 1990
6
AC ELECTRICAL CHARACTERISTICS
LIMITS
Tamb = +25°C
Tamb = 0°C to +70°C
SYMBOL
PARAMETER
TEST
VCC = +5.0V
VCC = +5.0V ± 10%
UNIT
CONDITION
CL = 50pF, RL = 500
MIN
TYP
MAX
MIN
MAX
fmax
Maximum clock frequency
Waveform 1
100
125
90
MHz
tPLH
tPHL
Propagation delay
CP to Qn
Waveform 1
4.5
6.0
6.5
8.0
9.0
10.5
4.0
5.5
10.0
11.5
ns
tPHL
Propagation delay
MR to Qn
Waveform 2
6.5
8.5
11.5
6.0
12.5
ns
tPZH
tPZL
Output enable time
to high or low level
Waveform 4
Waveform 5
3.5
5.5
5.0
7.0
8.0
10.0
2.5
4.5
8.5
11.0
ns
tPHZ
tPLZ
Output disable time
from high or low level
Waveform 4
Waveform 5
1.5
3.0
3.5
5.0
7.0
8.5
1.0
2.5
8.0
9.0
ns
tTHL
tTLH
Transition time
10% to 90%, 90% to 10%
Waveform 5
Waveform 4
2.0
4.0
5.0
7.5
8.0
10.0
2.0
4.0
8.5
11.0
ns
AC SETUP REQUIREMENTS
LIMITS
Tamb = +25°C
Tamb = 0°C to +70°C
SYMBOL
PARAMETER
TEST
VCC = +5.0V
VCC = +5.0V ± 10%
UNIT
CONDITION
CL = 50pF, RL = 500
CL= 50pF, RL = 500
MIN
TYP
MAX
MIN
MAX
tsu (H)
tsu (L)
Setup time, high or low level
Dn to CP
Waveform 3
2.5
3.0
4.0
ns
th (H)
th (L)
Hold time, high or low level
Dn to CP
Waveform 3
0
ns
tsu (H)
tsu (L)
Setup time, high or low level
E to CP
Waveform 3
4.5
7.5
5.0
8.5
ns
th (H)
th (L)
Hold time, high or low level
E to CP
Waveform 3
0
ns
tw (H)
tw (L)
CP Pulse width,
high or low
Waveform 1
3.0
6.0
3.0
6.0
ns
tw (H)
MR Pulse width, high
Waveform 2
3.5
ns
trec
Recovery time, MR to CP
Waveform 2
4.5
5.5
ns
AC WAVEFORMS
CP
VM
tw(H)
1/fmax
VM
tPLH
tw(L)
tPHL
Qn
SF00294
Waveform 1. Propagation delay for clock input to output, clock
pulse widths, and maximum clock frequency
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