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參數(shù)資料
| 型號(hào)： | 933821950623 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 編、解碼器及復(fù)用、解復(fù)用 |
| 英文描述： | F/FAST SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, MS-012AC, SOT-109-1, SO-16 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大小： | 150K |
| 代理商： | 933821950623 |
Philips Semiconductors
Product specification
74F258A
Quad 2-line to 1-line selector/multiplexer, inverting
(3-State)
2
1996 Jan 05
853-0361 16192
FEATURES
Multifunction capability
Non-inverting data path
3-State outputs
See 74F257A for non-inverting version
DESCRIPTION
The 74F258A has four identical 2-input multiplexers with 3-State
outputs which select 4 bits of data from two sources under control of
a common Select (S) input. The I0n inputs are selected when the
Select input is Low and the I1n inputs are selected when the Select
input is High. Data appears at the outputs in inverted form.
The 74F258A is the logical implementation of a 4-pole, 2-position
switch where the position of the switch is determined by the logic
level supplied to the Select input. Outputs are forced to a High
impedance ‘‘off” state when the Output Enable input (OE) is High. All
but one device must be in the High impedance state to avoid
currents that would exceed the maximum ratings if outputs are tied
together. Design of the output signals must ensure that there is no
overlap when outputs of 3-State devices are tied together.
PIN CONFIGURATION
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VCC
I0d
I1d
Yd
I0c
I1c
Yc
S
I0a
I1a
Ya
I0b
I1b
Yb
GND
OE
SF00815
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL SUPPLY
CURRENT (TOTAL)
74F258A
3.5ns
14mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
PKG.
DWG. #
16-pin plastic DIP
N74F258AN
SOT38-4
16-pin plastic SO
N74F258AD
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
I0n, I1n
Data inputs
1.0/1.0
20
A/0.6mA
S
Common select input
1.0/1.0
20
A/0.6mA
OE
Output Enable input (active Low)
1.0/1.0
20
A/0.6mA
Ya - Yd
Data outputs
150/40
3.0mA/24mA
NOTE:
One (1.0) FAST Unit Load is defined as: 20
A in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
OE
I0a I1a I0b I1b I0c I1c I0d I1d
15
2
3
5
6
11
10
14
13
479
12
1S
Ya
Yb
Yc
Yd
VCC=Pin 16
GND=Pin 8
SF00816
LOGIC SYMBOL (IEEE/IEC)
EN
15
G1
4
7
9
12
2
5
10
13
1
MUX
SF00817
1
3
6
11
14
1
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