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參數(shù)資料
| 型號： | 933794870602 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數(shù)移位寄存器 |
| 英文描述： | F/FAST SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, SC-603, SOT-146-1, DIP-20 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 148K |
| 代理商： | 933794870602 |
Philips Semiconductors
Product data
74F299
8-bit universal shift/storage register (3-State)
2
2003 Feb 05
FEATURES
Common parallel I/O for reduced pin count
Additional serial inputs and outputs for expansion
Four operating modes: Shift left, shift right, load and store
3-State outputs for bus-oriented applications
DESCRIPTION
The 74F299 is an 8-bit universal shift/storage register with 3-State
outputs. Four modes of operation are possible: Hold (store), shift
left, shift right and parallel load. The parallel load inputs and flip-flop
outputs are multiplexed to reduce the total number of package pins.
Additional outputs are provided for flip-flops Q0 and Q7 to allow
easy serial cascading. A separate active-LOW Master Reset is used
to reset the register.
The 74F299 contains eight edge-triggered D-type flip-flops and the
interstage logic necessary to perform synchronous shift left, shift
right, parallel load and hold operations. The type of operation is
determined by S0 and S1, as shown in the Function Table. All
flip-flop outputs are brought out through 3-State buffers to separate
I/O pins that also serve as data inputs in the parallel load mode.
Q0 and Q7 are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on MR overrides the Select and CP inputs and resets
the flip-flops. All other state changes are initiated by the rising edge
of the clock. Inputs can change when the clock is in either state
provided only that the recommended set-up and hold times, relative
to the rising edge of clock are observed.
A HIGH signal on either OE0 or OE1 disables the 3-State buffers
and puts the I/O pins in the high impedance state. In this condition
the shift, hold, load and reset operations can still occur. The 3-State
buffers are also disabled by High signals on both S0 and S1 in
preparation for a parallel load operation.
PIN CONFIGURATION
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
VCC
S1
DS7
Q7
I/O7
I/O5
I/O3
I/O1
DS0
S0
I/O6
I/O4
I/O2
I/O0
Q0
OE0
OE1
MR
GND
CP
SF00865
TYPE
TYPICAL fMAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F299
115 MHz
58 mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL
RANGE
VCC = 5 V ±10%,
Tamb = 0 °C to +70 °C
PKG DWG #
20-pin plastic DIP
N74F299N
SOT146-1
20-pin plastic SOL
N74F299D
SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH / LOW
LOAD VALUE
HIGH / LOW
DS0
Serial data input for right shift
1.0 / 1.0
20
A / 0.6 mA
DS7
Serial data input for left shift
1.0 / 1.0
20
A / 0.6 mA
S0, S1
Mode select inputs
1.0 / 2.0
20
A / 1.2 mA
CP
Clock pulse input (Active rising edge)
1.0 / 1.0
20
A / 0.6 mA
MR
Asynchronous Master Reset input (Active LOW)
1.0 / 1.0
20
A / 0.6 mA
OE0, OE1
Output Enable input (Active LOW)
1.0 / 1.0
20
A / 0.6 mA
Q0, Q7
Serial outputs
50 / 33
1.0 mA / 20 mA
I/On
Multiplexed parallel data inputs
3.5 / 1.0
70
A / 0.6 mA
I/On
3-State parallel outputs
150 / 40
3.0 mA / 24 mA
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20
A in the HIGH State and 0.6 mA in the LOW state.
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