參數(shù)資料
型號(hào)： 933784230602
廠商： NXP SEMICONDUCTORS
元件分類： 計(jì)數(shù)移位寄存器
英文描述： F/FAST SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16
封裝： 3.90 MM, PLASTIC, MS-012AC, SOT-109-1, SO-16
文件頁(yè)數(shù)： 6/10頁(yè)
文件大?。?/td> 99K
代理商： 933784230602
Philips Semiconductors
Product specification
74F194
4-bit bidirectional universal shift register
April 4, 1989
5
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS1
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS1
MIN
TYP2
MAX
UNIT
VO
High level output voltage3
VCC = MIN, VIL = MAX
±10%VCC
2.5
V
VOH
High-level output voltage3
VIH = MIN, IOH = MAX
±5%VCC
2.7
3.4
V
VO
Low level output voltage
VCC = MIN, VIL = MAX
±10%VCC
0.30
0.50
V
VOL
Low-level output voltage
VIH = MIN, IOL = MAX
±5%VCC
0.30
0.50
V
VIK
Input clamp voltage
VCC = MIN, II = IIK
–0.73
–1.2
V
II
Input current at maximum input voltage
VCC = MAX, VI = 7.0V
100
A
IIH
High-level input current
VCC = MAX, VI = 2.7V
20
A
IIL
Low-level input current
VCC = MAX, VI = 0.5V
–0.6
mA
IOS
Short-circuit output current4
VCC = MAX
–60
–150
mA
ICC
Supply current (total)5
VCC = MAX
33
46
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Output High state will change to Low stat if an external voltage of less than 0.0V is applied.
4. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
5. With all outputs open, Di inputs grounded and a 4.5V applied to S0, S1, MR and the serial inputs, ICC is tested with a momentary ground,
then 4.5V applied to CP.
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
VCC = +5.0V
Tamb = +25°C
CL = 50pF, RL = 500
VCC = +5.0V ± 10%
Tamb = 0°C to +70°C
CL = 50pF, RL = 500
UNIT
MIN
TYP
MAX
MIN
MAX
fMAX
Maximum clock frequency
Waveform 1
105
150
90
MHz
tPLH
tPHL
Propagation delay
CP to Qn
Waveform 1
3.5
5.2
5.5
7.0
3.5
8.0
ns
tPHL
Propagation delay
MR to Qn
Waveform 2
4.5
8.6
12.0
4.5
14.0
ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
VCC = +5.0V
Tamb = +25°C
CL = 50pF, RL = 500
VCC = +5.0V ± 10%
Tamb = 0°C to +70°C
CL = 50pF, RL = 500
UNIT
MIN
TYP
MAX
MIN
MAX
tS(H)
tS(L)
Setup time, High or Low
Dn, DSL, DSR to CP
Waveform 3
4.0
ns
th(H)
th(L)
Hold time, High or Low
Dn, DSL, DSR to CP
Waveform 3
0
1.0
ns
tS(H)
tS(L)
Setup time, High or Low
Sn to CP
Waveform 3
8.0
9.0
8.0
ns
th(H)
th(L)
Hold time, High or Low
Sn to CP
Waveform 3
0
ns
tW(H)
CP Pulse width, High
Waveform 1
5.0
5.5
ns
tW(L)
MR Pulse width, Low
Waveform 2
5.0
ns
tREC
Recovery time, MR to CP
Waveform 2
7.0
8.0
ns
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