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參數(shù)資料
| 型號(hào)： | 933783380005 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 80K |
| 代理商： | 933783380005 |
December 1990
9
Philips Semiconductors
Product specication
Presettable synchronous 4-bit binary
counter; asynchronous reset
74HC/HCT161
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (
ICC) for a unit load of 1 is given in the family specifications.
To determine
ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
INPUT
UNIT LOAD COEFFICIENT
MR
0.95
CP
1.10
CEP
0.25
Dn
0.25
CET
0.75
PE
0.30
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT
VCC
(V)
WAVEFORMS
+25
40 to +85
40 to +125
min.
typ.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
CP to Qn
23
43
54
65
ns
4.5
Fig.8
tPHL/ tPLH
propagation delay
CP to TC
28
48
60
72
ns
4.5
Fig.8
tPHL
propagation delay
MR to Qn
29
46
58
69
ns
4.5
Fig.9
tPHL
propagation delay
MR to TC
30
51
64
77
ns
4.5
Fig.9
tPHL/ tPLH
propagation delay
CET to TC
17
35
44
53
ns
4.5
Fig.10
tTHL/ tTLH
output transition time
7
15
19
22
ns
4.5
Figs 8 and 10
tW
clock pulse width
HIGH or LOW
16
7
20
24
ns
4.5
Fig.8
tW
master reset pulse
width; LOW
20
10
25
30
ns
4.5
Fig.9
trem
removal time
MR to CP
20
6
25
30
ns
4.5
Fig.9
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