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參數(shù)資料
| 型號： | 933774940518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, MO-047AC, SOT-187-2, LCC-44 |
| 文件頁數(shù)： | 16/34頁 |
| 文件大?。?/td> | 313K |
| 代理商： | 933774940518 |
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Philips Semiconductors
Product specification
SCN2681
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
23
Output Port Notes
The output ports are controlled from three places: the OPCR
register, the OPR register, and the MR registers. The OPCR
register controls the source of the data for the output ports OP2
through OP7. The data source for output ports OP0 and OP1 is
controlled by the MR and CR registers. When the OPR is the
source of the data for the output ports, the data at the ports is
inverted from that in the OPR register. The content of the OPR
register is controlled by the “Set Output Port Bits Command” and the
“Reset Output Bits Command”. These commands are at E and F,
respectively. When these commands are used, action takes place
only at the bit locations where ones exist. For example, a one in bit
location 5 of the data word used with the “Set Output Port Bits”
command will result in OPR5 being set to one. The OP5 would then
be set to zero (VSS). Similarly, a one in bit position 5 of the data
word associated with the “Reset Output Ports Bits” command would
set OPR5 to zero and, hence, the pin OP5 to a one (VDD).
The CTS, RTS, CTS Enable Tx signals
CTS (Clear To Send) is usually meant to be a signal to the
transmitter meaning that it may transmit data to the receiver. The
CTS input is on pin IP0 for TxA and on IP1 for TxB. The CTS signal
is active low; thus, it is called CTSAN for TxA and CTSBN for TxB.
RTS is usually meant to be a signal from the receiver indicating that
the receiver is ready to receive data. It is also active low and is,
thus, called RTSAN for RxA and RTSBN for RxB. RTSAN is on pin
op0 and RTSBN is on OP1. A receiver’s RTS output will usually be
connected to the CTS input of the associated transmitter. Therefore,
one could say that RTS and CTS are different ends of the same
wire!
MR2(4) is the bit that allows the transmitter to be controlled by the
CTS pin (IP0 or IP1). When this bit is set to one AND the CTS input
is driven high, the transmitter will stop sending data at the end of the
present character being serialized. It is usually the RTS output of
the receiver that will be connected to the transmitter’s CTS input.
The receiver will set RTS high when the receiver FIFO is full AND
the start bit of the fourth character is sensed. Transmission then
stops with four valid characters in the receiver. When MR2(4) is set
to one, CTSN must be at zero for the transmitter to operate. If
MR2(4) is set to zero, the IP pin will have no effect on the operation
of the transmitter.
MR1(7) is the bit that allows the receiver to control OP0. When OP0
(or OP1) is controlled by the receiver, the meaning of that pin will be
RTS. However, a point of confusion arises in that OP0 (or OP1)
may also be controlled by the transmitter. When the transmitter is
controlling this pin, its meaning is not RTS at all. It is, rather, that
the transmitter has finished sending its last data byte. Programming
the OP0 or OP1 pin to be controlled by the receiver and the
transmitter at the same time is allowed, but would usually be
incompatible.
RTS is expressed at the OP0 or OP1 pin which is still an output port.
Therefore, the state of OP0 or OP1 should be set low for the
receiver to generate the proper RTS signal. The logic at the output
is basically a NAND of the OPR register and the RTS signal as
generated by the receiver. When the RTS flow control is selected
via the MR(7) bit state of the OPR register is not changed.
Terminating the use of “Flow Control” (via the MR registers) will
return the OP0 or OP1 pins to the control of the OPR register.
Transmitter Disable Note
The sequence of instructions enable transmitter — load transmit
holding register — disable transmitter will result in nothing being
sent if the time between the end of loading the transmit holding
register and the disable command is less that 3/16 bit time in the
16x mode or one bit time in the 1x mode. Also, if the transmitter,
while in the enabled state and underrun condition, is immediately
disabled after a single character is loaded to the transmit holding
register, that character will not be sent.
In general, when it is desired to disable the transmitter before the
last character is sent AND the TxEMT bit is set in the status register
(TxEMT is always set if the transmitter has underrun or has just
been enabled), be sure the TxRDY bit is active immediately before
issuing the transmitter disable instruction. TxRDY sets at the end of
the “start bit” time. It is during the start bit that the data in the
transmit holding register is transferred to the transmit shift register.
Non-standard baud rates are available as shown in Table 5 below,
via the BRG Test function.
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