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參數(shù)資料
| 型號： | 933715220112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 16 X 4 OTHER FIFO, 120 ns, PDSO16 |
| 封裝： | 3.90 MM, PLASITC, MS-012AC, SOT-109-1, SO-16 |
| 文件頁數(shù)： | 22/25頁 |
| 文件大?。?/td> | 178K |
| 代理商： | 933715220112 |
6
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
4.
CPU Core
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure cor-
rect program execution. The CPU must therefore be able to access memories, perform calculations, control
peripherals, and handle interrupts.
4.1
Architectural Overview
Figure 4-1.
Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories
and buses for program and data. Instructions in the program memory are executed with a single level pipelining.
While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle. The program memory is In-System reprogrammable
Flash memory.
The fast-access Register File contains 16 x 8-bit general purpose working registers with a single clock cycle
access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two oper-
ands are output from the Register File, the operation is executed, and the result is stored back in the Register File
– in one clock cycle.
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
16 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
Data Bus 8-bit
Data
SRAM
Dir
ec
tA
ddr
essing
In
d
ir
e
ct
A
ddr
essing
Interrupt
Unit
Watchdog
Timer
Analog
Comparator
Timer/Counter 0
ADC
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| 935189350118 | 16 X 4 OTHER FIFO, 600 ns, PDSO16 |
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