參數(shù)資料
型號： 933714540653
廠商： NXP SEMICONDUCTORS
元件分類： 計數(shù)器
英文描述： HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
封裝： SOT-109, SO-16
文件頁數(shù)： 14/16頁
文件大?。?/td> 173K
代理商： 933714540653
December 1990
7
Philips Semiconductors
Product specication
Presettable synchronous 4-bit binary
counter; synchronous reset
74HC/HCT163
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr =tf = 6 ns; CL =50pF
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to +85 40 to +125
min.
typ.
max.
min.
max. min. max.
tPHL/ tPLH
propagation delay
CP to Qn
55
20
16
185
37
31
230
46
39
280
56
48
ns
2.0
4.5
6.0
Fig.8
tPHL/ tPLH
propagation delay
CP to TC
69
25
20
215
43
37
270
54
46
320
65
55
ns
2.0
4.5
6.0
Fig.8
tPHL/ tPLH
propagation delay
CET to TC
36
13
10
120
24
20
150
30
26
180
36
31
ns
2.0
4.5
6.0
Fig.9
tTHL/ tTLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Figs 8 and 9
tW
clock pulse width
HIGH or LOW
80
16
14
17
6
5
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.8
tsu
set-up time
MR, Dn to CP
80
16
14
17
6
5
100
20
17
120
24
20
ns
2.0
4.5
6.0
Figs 10 and 11
tsu
set-up time
PE to CP
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.10
tsu
set-up time
CEP, CET to CP
175
35
30
58
21
17
220
44
37
265
53
45
ns
2.0
4.5
6.0
Fig.12
th
hold time
Dn, PE, CEP,
CET, MR to CP
0
14
5
4
0
ns
2.0
4.5
6.0
Figs 10, 11 and 12
fmax
maximum clock pulse
frequency
5
27
32
15
46
55
4
22
26
4
18
21
MHz
2.0
4.5
6.0
Fig.8
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