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參數(shù)資料
| 型號(hào)： | 933669420652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 鎖存器 |
| 英文描述： | HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP16 |
| 封裝： | SOT-38-1, DIP-16 |
| 文件頁(yè)數(shù)： | 14/14頁(yè) |
| 文件大?。?/td> | 152K |
| 代理商： | 933669420652 |
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December 1990
9
Philips Semiconductors
Product specication
Quad D-type ip-op; positive-edge trigger; 3-state
74HC/HCT173
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr =tf = 6 ns; CL =50pF
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT
VCC
(V)
WAVEFORMS
+25
40 to +85 40 to +125
min.
typ.
max.
min.
max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
20
40
50
60
ns
4.5
Fig.6
tPHL
propagation delay
MR to Qn
20
37
46
56
ns
4.5
Fig.7
tPZH/ tPZL
3-state output enable time
OEn to Qn
20
35
44
53
ns
4.5
Fig.8
tPHZ/ tPLZ
3-state output disable time
OEn to Qn
19
30
38
45
ns
4.5
Fig.8
tTHL/ tTLH
output transition time
5
12
15
19
ns
4.5
Fig.6
tW
clock pulse width
HIGH or LOW
16
7
20
24
ns
4.5
Fig.6
tW
master reset pulse
width; HIGH
15
6
19
22
ns
4.5
Fig.7
trem
removal time
MR to CP
12
2
15
18
ns
4.5
Fig.7
tsu
set-up time
En to CP
22
13
28
33
ns
4.5
Fig.9
tsu
set-up time
Dn to CP
12
7
15
18
ns
4.5
Fig.9
th
hold time
En to CP
0
6
0
ns
4.5
Fig.9
th
hold time
Dn to CP
0
3
0
ns
4.5
Fig.9
fmax
maximum clock pulse
frequency
30
80
24
20
MHz
4.5
Fig.6
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