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參數(shù)資料
| 型號： | 933529770652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數(shù)器 |
| 英文描述： | 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 152K |
| 代理商： | 933529770652 |
January 1995
2
Philips Semiconductors
Product specication
4-bit synchronous binary counter with
asynchronous reset
HEF40161B
MSI
DESCRIPTION
The HEF40161B is a fully synchronous edge-triggered
4-bit binary counter with a clock input (CP), an overriding
asynchronous master reset (MR), four parallel data inputs
(P0 to P3), three synchronous mode control inputs (parallel
enable (PE), count enable parallel (CEP) and count enable
trickle (CET)), buffered outputs from all four bit positions
(O0 to O3) and a terminal count output (TC).
Operation is fully synchronous (except for the MR input)
and occurs on the LOW to HIGH transition of CP. When
PE is LOW, the next LOW to HIGH transition of CP loads
data into the counter from P0 to P3 regardless of the levels
of CEP and CET inputs.
When PE is HIGH, the next LOW to HIGH transition of CP
advances the counter to its next state only if both CEP and
CET are HIGH; otherwise, no change occurs in the state
of the counter. TC is HIGH when the state of the counter is
15 (O1 to O3 = HIGH) and when CET is HIGH. A LOW on
MR sets all outputs (O0 to O3 and TC) LOW, independent
of the state of all other inputs. Multistage synchronous
counting is possible without additional components by
using a carry look-ahead counting technique; in this case,
TC is used to enable successive cascaded stages. CEP,
CET and PE must be stable only during the set-up time
before the LOW to HIGH transition of CP.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
Fig.1 Functional diagram.
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