參數(shù)資料
型號： 933373470653
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
封裝： PLASTIC, SOT-109-1, SO-16
文件頁數(shù)： 4/5頁
文件大?。?/td> 61K
代理商： 933373470653
January 1995
4
Philips Semiconductors
Product specication
Quadruple D-type ip-op
HEF40175B
MSI
AC CHARACTERISTICS
VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN.
TYP. MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
CP
→ On, On
5
80
160 ns
53 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
35
70 ns
24 ns
+ (0,23 ns/pF) CL
15
25
50 ns
17 ns
+ (0,16 ns/pF) CL
5
70
140 ns
43 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
30
65 ns
19 ns
+ (0,23 ns/pF) CL
15
25
45 ns
17 ns
+ (0,16 ns/pF) CL
MR
→ On
5
75
155 ns
48 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
30
65 ns
19 ns
+ (0,23 ns/pF) CL
15
25
50 ns
17 ns
+ (0,16 ns/pF) CL
MR
→ On
5
70
140 ns
43 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
30
65 ns
19 ns
+ (0,23 ns/pF) CL
15
25
50 ns
17 ns
+ (0,16 ns/pF) CL
Output transition times
5
60
120 ns
10 ns
+ (1,0 ns/pF) CL
HIGH to LOW
10
tTHL
30
60 ns
9 ns
+ (0,42 ns/pF) CL
15
20
40 ns
6 ns
+ (0,28 ns/pF) CL
5
60
120 ns
10 ns
+ (1,0 ns/pF) CL
LOW to HIGH
10
tTLH
30
60 ns
9 ns
+ (0,42 ns/pF) CL
15
20
40 ns
6 ns
+ (0,28 ns/pF) CL
Set-up time
5
60
30
ns
see also waveforms Fig.4
Dn → CP
10
tsu
20
10
ns
15
5
ns
Hold time
5
25
5ns
Dn → CP
10
thold
10
0
ns
15
10
0
ns
Minimum clock
5
90
45
ns
pulse width; LOW
10
tWCPL
35
15
ns
15
25
10
ns
Minimum MR pulse
5
80
40
ns
width; LOW
10
tWMRL
30
15
ns
15
20
10
ns
Recovery time
5
0
30
ns
for MR
10
tRMR
0
20
ns
15
0
15
ns
Maximum clock
5
11
MHz
pulse frequency
10
fmax
15
30
MHz
15
20
45
MHz
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