參數(shù)資料
型號(hào)： 933373410653
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 總線收發(fā)器
英文描述： HEX 1-BIT DRIVER, INVERTED OUTPUT, PDSO16
封裝： PLASTIC, SOT-109-1, SO-16
文件頁(yè)數(shù)： 4/4頁(yè)
文件大?。?/td> 39K
代理商： 933373410653
January 1995
4
Philips Semiconductors
Product specication
3-state hex inverting buffer
HEF40098B
buffers
AC CHARACTERISTICS
VSS =0V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
In → On
5
80
160
ns
70 ns
+ (0,20 ns/pF) CL
HIGH to LOW
10
tPHL
35
70
ns
31 ns
+ (0,08 ns/pF) CL
15
25
50
ns
22 ns
+ (0,06 ns/pF) CL
5
65
130
ns
50 ns
+ (0,30 ns/pF) CL
LOW to HIGH
10
tPLH
30
60
ns
24 ns
+ (0,13 ns/pF) CL
15
25
50
ns
23 ns
+ (0,05 ns/pF) CL
Output transition times
5
30
60
ns
15 ns
+ (0,30 ns/pF) CL
HIGH to LOW
10
tTHL
15
30
ns
10 ns
+ (0,11 ns/pF) CL
15
10
20
ns
7 ns
+ (0,07 ns/pF) CL
535
70
ns
10 ns
+ (0,50 ns/pF) CL
LOW to HIGH
10
tTLH
20
40
ns
8 ns
+ (0,24 ns/pF) CL
15
30
ns
6 ns
+ (0,18 ns/pF) CL
3-state propagation delays
Output disable times
EO2, EO4 → On
545
85
ns
HIGH
10
tPHZ
35
65
ns
15
30
60
ns
5
65
135
ns
LOW
10
tPLZ
40
80
ns
15
35
70
ns
Output enable times
EO2, EO4 → On
5
70
140
ns
HIGH
10
tPZH
35
75
ns
15
30
65
ns
5
90
185
ns
LOW
10
tPZL
40
85
ns
15
35
70
ns
VDD
V
TYPICAL FORMULA FOR P (
W)
Dynamic power
5
5 000 fi +∑ (foCL) × VDD2
where
dissipation per
10
22 800 fi +∑ (foCL) × VDD2
fi = input freq. (MHz)
package (P)
15
81 000 fi +∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load cap. (pF)
∑ (f
oCL) = sum of outputs
VDD = supply voltage (V)
相關(guān)PDF資料
PDF描述
0553-0043-DC ISDN TRANSFORMER
933373430652 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
933529770652 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16
935019370112 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16
933334360652 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16
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