參數(shù)資料
型號(hào)： 933373250653
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 計(jì)數(shù)器
英文描述： 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
封裝： PLASTIC, SOT-109-1, SO-16
文件頁(yè)數(shù)： 2/7頁(yè)
文件大?。?/td> 62K
代理商： 933373250653
January 1995
2
Philips Semiconductors
Product specication
Dual binary counter
HEF4520B
MSI
DESCRIPTION
The HEF4520B is a dual 4-bit internally synchronous
binary counter. The counter has an active HIGH clock
input (CP0) and an active LOW clock input (CP1), buffered
outputs from all four bit positions (O0 to O3) and an active
HIGH overriding asynchronous master reset input (MR).
The counter advances on either the LOW to HIGH
transition of the CP0 input if CP1 is HIGH or the HIGH to
LOW transition of the CP1 input if CP0 is low. Either CP0 or
CP1 may be used as the clock input to the counter and the
other clock input may be used as a clock enable input. A
HIGH on MR resets the counter (O0 to O3 = LOW)
independent of CP0, CP1.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
Fig.1 Functional diagram.
HEF4520BP(N):
16-lead DIL; plastic
(SOT38-1)
HEF4520BD(F):
16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4520BT(D):
16-lead SO; plastic (SOT109-1)
(SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
CP0A,CP0B
clock inputs (L to H triggered)
CP1A, CP1B
clock inputs (H to L triggered)
MRA,MRB
master reset inputs
O0A to O3A
outputs
O0B to O3B
outputs
相關(guān)PDF資料
PDF描述
933373250652 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
933373280653 4000/14000/40000 SERIES, 8-BIT ENCODER, PDSO16
933373280652 4000/14000/40000 SERIES, 8-BIT ENCODER, PDSO16
933373300652 4000/14000/40000 SERIES, SEVEN SEGMENT DECODER/DRIVER, CONFIGURABLE OUTPUT, PDSO16
933373310652 4000/14000/40000 SERIES, OTHER DECODER/DRIVER, TRUE OUTPUT, PDSO16
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