參數(shù)資料
型號(hào)： 933373060652
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： 4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16
封裝： PLASTIC, SOT-109-1, SO-16
文件頁(yè)數(shù)： 4/7頁(yè)
文件大?。?/td> 68K
代理商： 933373060652
January 1995
4
Philips Semiconductors
Product specication
Quadruple D-type register with 3-state outputs
HEF4076B
MSI
FUNCTION TABLE
INPUTS
OUTPUTS
MR
CP
ED0
ED1
Dn
On
HX
X
L
H
X
no change
L
X
H
X
no change
LL
L
H
LL
L
X
no change
Notes
1. EO0 = EO1 = LOW
When either EO0 or EO1 is HIGH, the outputs are
disabled (high impedance OFF-state).
H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
= negative-going transition
AC CHARACTERISTICS
VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns; see also waveforms Fig.4
VDD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
CP
→ On
5
150
305
ns
123 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
60
120
ns
49 ns
+ (0,23 ns/pF) CL
15
45
85
ns
37 ns
+ (0,16 ns/pF) CL
5
160
320
ns
133 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
65
130
ns
54 ns
+ (0,23 ns/pF) CL
15
45
90
ns
37 ns
+ (0,16 ns/pF) CL
MR
→ On
5
95
190
ns
68 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
40
85
ns
29 ns
+ (0,23 ns/pF) CL
15
30
65
ns
22 ns
+ (0,16 ns/pF) CL
Output transition times
5
60
120
ns
10 ns
+ (1,0 ns/pF) CL
HIGH to LOW
10
tTHL
30
60
ns
9 ns
+ (0,42 ns/pF) CL
15
20
40
ns
6 ns
+ (0,28 ns/pF) CL
5
60
120
ns
10 ns
+ (1,0 ns/pF) CL
LOW to HIGH
10
tTLH
30
60
ns
9 ns
+ (0,42 ns/pF) CL
15
20
40
ns
6 ns
+ (0,28 ns/pF) CL
3-state propagation times
Output disable times
5
50
105
ns
EOn → On
10
tPHZ
35
70
ns
HIGH
15
30
65
ns
545
90
ns
LOW
10
tPLZ
30
65
ns
15
30
60
ns
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