參數(shù)資料
型號(hào)： 933373000652
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 門(mén)電路
英文描述： 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, PDSO14
封裝： PLASTIC, SOT-108-1, SO-14
文件頁(yè)數(shù)： 3/7頁(yè)
文件大小： 115K
代理商： 933373000652
January 1995
3
Philips Semiconductors
Product specication
Hex inverter
HEF4069UB
gates
AC CHARACTERISTICS
VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
TYP. MAX.
TYPICAL EXTRAPOLATION FORMULA
Propagation delays
5
45
90 ns
18 ns
+ (0,55 ns/pF) CL
In → On
10
tPHL
20
40 ns
9 ns
+ (0,23 ns/pF) CL
HIGH to LOW
15
25 ns
7 ns
+ (0,16 ns/pF) CL
540
80 ns
13 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
20
40 ns
9 ns
+ (0,23 ns/pF) CL
15
30 ns
7 ns
+ (0,16 ns/pF) CL
Output transition times
5
60
120 ns
10 ns
+ (1,0 ns/pF) CL
HIGH to LOW
10
tTHL
30
60 ns
9 ns
+ (0,42 ns/pF) CL
15
20
40 ns
6 ns
+ (0,28 ns/pF) CL
5
60
120 ns
10 ns
+ (1,0 ns/pF) CL
LOW to HIGH
10
tTLH
30
60 ns
9 ns
+ (0,42 ns/pF) CL
15
20
40 ns
6 ns
+ (0,28 ns/pF) CL
VDD
V
TYPICAL FORMULA FOR P (
W)
Dynamic power
5
600 fi +∑ (foCL) × VDD2
where
dissipation per
10
4 000 fi +∑ (foCL) × VDD2
fi = input freq. (MHz)
package (P)
15
22 000 fi +∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (f
oCL) = sum of outputs
VDD = supply voltage (V)
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