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參數(shù)資料
| 型號： | 933334250652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | 4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP16 |
| 封裝： | PLASTIC, SOT-38-1, DIP-16 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 68K |
| 代理商： | 933334250652 |
January 1995
2
Philips Semiconductors
Product specication
Quadruple D-type register with 3-state outputs
HEF4076B
MSI
DESCRIPTION
The HEF4076B is a quadruple edge-triggered D-type
flip-flop with four data inputs (D0 to D3), two active LOW
data enable inputs (ED0 and ED1), a common clock input
(CP), four 3-state outputs (O0 to O3), two active LOW
output enable inputs (EO0 and EO1), and an overriding
asynchronous master reset input (MR).
Information on D0 to D3 is stored in the four flip-flops on the
LOW to HIGH transition of CP if both ED0 and ED1 are
LOW. A HIGH on either ED0 or ED1 prevents the flip-flops
from changing on the LOW to HIGH transition of CP,
independent of the information on D0 to D3. When both
EO0 and EO1 are LOW, the contents of the four flip-flops
are available at O0 to O3. A HIGH on either EO0 or
EO1 forces O0 to O3 into the high impedance OFF-state. A
HIGH on MR resets all four flip-flops, independent of all
other input conditions.
Fig.1 Functional diagram.
HEF4076BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4076BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4076BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
D0 to D3
data inputs
ED0, ED1
data enable inputs (active LOW)
EO0, EO1
output enable inputs (active LOW)
CP
clock input (LOW to HIGH, edge-triggered)
MR
master reset input
O0 to O3
data outputs
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
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