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參數(shù)資料
| 型號： | 933324210652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 門電路 |
| 英文描述： | 4000/14000/40000 SERIES, TRIPLE 1-INPUT INVERT GATE, PDIP14 |
| 封裝： | PLASTIC, SOT-27-1, DIP-14 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大小： | 119K |
| 代理商： | 933324210652 |
Philips Semiconductors
Product specification
Logic level TOPFET
BUK138-50DL
D-PAK version of BUK117-50DL
INPUT CHARACTERISTICS
The supply for the logic and overload protection is taken from the input.
Limits are for -40C
≤ T
mb
≤ 150C; typicals are for T
mb = 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
IS(TO)
Input threshold voltage
V
DS = 5 V; ID = 1 mA
0.6
-
2.4
V
T
mb = 25C
1.1
1.6
2.1
V
I
IS
Input supply current
normal operation;
V
IS = 5 V
100
220
400
A
V
IS = 4 V
80
195
330
A
I
ISL
Input supply current
protection latched;
V
IS = 5 V
200
400
650
A
V
IS = 3 V
130
250
430
A
V
ISR
Protection reset voltage
1
reset time t
r
≥ 100 s
1.5
2
2.9
V
t
lr
Latch reset time
V
IS1 = 5 V, VIS2 < 1 V
10
40
100
s
V
(CL)IS
Input clamping voltage
I
I = 1.5 mA
5.5
-
8.5
V
R
IG
Input series resistance
2
T
mb = 25C
-
33
-
k
to gate of power MOSFET
SWITCHING CHARACTERISTICS
T
mb = 25 C; VDD = 13 V; resistive load RL = 4
. Refer to waveform figure and test circuit.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
t
d on
Turn-on delay time
V
IS = 5 V
-
10
20
s
t
r
Rise time
-
20
40
s
t
d off
Turn-off delay time
V
IS = 0 V
-
30
60
s
t
f
Fall time
-
20
40
s
1 The input voltage below which the overload protection circuits will be reset.
2 Not directly measureable from device terminals.
May 2001
4
Rev 1.300
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