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參數(shù)資料
| 型號(hào)： | 933296760652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | PLASTIC, SOT-38-1, DIP-16 |
| 文件頁(yè)數(shù)： | 2/5頁(yè) |
| 文件大?。?/td> | 61K |
| 代理商： | 933296760652 |
January 1995
2
Philips Semiconductors
Product specication
Quadruple D-type ip-op
HEF40175B
MSI
DESCRIPTION
The HEF40175B is a quadruple edge-triggered D-type
flip-flop with four data inputs (D0 to D3), a clock input (CP),
an overriding asynchronous master reset input (MR), four
buffered outputs (O0 to O3), and four complementary
buffered outputs (O0 to O3). Information on D0 to D3 is
transferred to O0 to O3 on the LOW to HIGH transition of
CP if MR is HIGH. When LOW, MR resets all flip-flops
(O0 to O3 = LOW, O0 to O3 = HIGH), independent of CP
and D0 to D3.
Fig.1 Functional diagram.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
HEF40175BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF40175BD(F):
16-lead DIL; ceramic (cerdip)
(SOT74)
HEF40175BT(D):
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
FUNCTION TABLE
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
= negative-going transition
D0 to D3
data inputs
CP
clock input (LOW to HIGH; edge-triggered)
MR
master reset input (active LOW)
O0 to O3
buffered outputs
O0 to O3
complementary buffered outputs
INPUTS
OUTPUTS
CP
D
MR
O
HH
H
L
LH
L
H
X
H
no change
XX
L
H
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