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參數(shù)資料
| 型號： | 933296660652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數(shù)器 |
| 英文描述： | 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP16 |
| 封裝： | PLASTIC, SOT-38-1, DIP-16 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 184K |
| 代理商： | 933296660652 |
January 1995
2
Philips Semiconductors
Product specication
Synchronous up/down counter,
binary/decade counter
HEF4029B
MSI
DESCRIPTION
The HEF4029B is a synchronous edge-triggered up/down
4-bit binary/BCD decade counter with a clock input (CP),
an active LOW count enable input (CE), an up/down
control input (UP/DN), a binary/decade control input
(BIN/DEC), an overriding asynchronous active HIGH
parallel load input (PL), four parallel data inputs (P0 to P3),
four parallel buffered outputs (O0 to O3) and an active
LOW terminal count output (TC).
Information on P0 to P3 is asynchronously loaded into the
counter while PL is HIGH, independent of CP.
The counter is advanced one count on the LOW to HIGH
transition of CP when CE and PL are LOW. The TC signal
is normally HIGH and goes LOW when the counter
reaches its maximum count in the UP mode, or the
minimum count in the DOWN mode provided CE is LOW.
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
HEF4029BP(N):
16-lead DIL; plastic
(SOT38-1)
HEF4029BD(F):
16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4029BT(D):
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PINNING
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
PL
parallel load input
P0 to P3
parallel data inputs
BIN/DEC
binary/decade control input
UP/DN
up/down control input
CE
count enable input (active LOW)
CP
clock input (LOW to HIGH, edge triggered)
O0 to O3
buffered parallel outputs
TC
terminal count output (active LOW)
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