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參數(shù)資料
| 型號(hào)： | 9314FMQB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad Latch |
| 中文描述： | 93 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDFP16 |
| 封裝： | CERAMIC, FP-16 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 123K |
| 代理商： | 9314FMQB |
Switching Characteristics
V
CC
e a
5.0V, T
A
e a
25
§
C (See Section 1 for waveforms and load configurations)
Symbol
Parameter
C
L
e
15 pF
Units
Min
Max
t
PLH
t
PHL
Propagation Delay
E to Q
n
24
24
ns
t
PLH
t
PHL
Propagation Delay
D
n
to Q
n
12
24
ns
t
PLH
Propagation Delay
MR to Q
n
18
ns
t
PHL
Propagation Delay
S
n
to Q
n
24
ns
Functional Description
The ’9314 consists of four latches with a common active
LOW Enable input and active LOW Master Reset input.
When the Enable goes HIGH, data present in the latches is
stored and the state of the latch is no longer affected by the
S
n
and D
n
inputs. The Master Reset when activated over-
rides all other input conditions forcing all latch outputs LOW.
Each of the four latches can be operated in one of two
modes:
D-TYPE LATCHDFor D-type operation the S input of a latch
is held LOW. While the common Enable is active the latch
output follows the D input. Information present at the latch
output is stored in the latch when the Enable goes HIGH.
SET/RESET LATCHDDuring set/reset operation when the
common Enable is LOW a latch is reset by a LOW on the D
input, and can be set by a LOW on the S input if the D input
is HIGH. If both S and D inputs are LOW, the D input will
dominate and the latch will be reset. When the Enable goes
HIGH, the latch remains in the last state prior to disable-
ment. The two modes of latch operation are shown in the
Truth Table.
Truth Table
MR
E
D
S
Q
n
Operation
H
H
H
L
L
H
L
H
X
L
L
X
L
H
D Mode
Q
n
b
1
H
H
H
H
H
L
L
L
L
H
L
H
L
H
X
L
L
H
H
X
L
H
L
R/S Mode
Q
n
b
1
Q
n
b
1
L
X
X
X
L
Reset
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Q
n
b
1
e
Previous Output State
Q
n
e
Present Output State
3
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參數(shù)描述 |
|---|---|
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