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參數(shù)資料
| 型號(hào)： | 92HD005XX5PRGXYYX |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 編解碼器 |
| 英文描述： | 4-CHANNEL HD AUDIO CODEC WITH QUAD DIGITAL MICROPHONE INTERFACE |
| 中文描述： | PCM CODEC, PQFP48 |
| 封裝： | ROHS COMPLIANT, LQFP-48 |
| 文件頁(yè)數(shù)： | 15/205頁(yè) |
| 文件大?。?/td> | 1412K |
| 代理商： | 92HD005XX5PRGXYYX |
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92HD005/92HD005D
4-CHANNEL HD AUDIO CODEC WITH QUAD DIGITAL MICROPHONE INTERFACE
PC AUDIO
IDT
15
92HD005/92HD005D
V 1.0 12/06
4-CHANNEL HD AUDIO CODEC WITH QUAD DIGITAL MICROPHONE INTERFACE
Table 1. 92HD005/92HD005D Valid Digital Microphone Configurations
Table 2. DMIC_CLK, DMIC_0 and DMIC_1 Operation During Power States
Digital
Mics
0
Data Sample
ADC
Conn.
N/A
Notes
N/A
No Digital Microphones
Available on either DMIC_0 or DMIC_1
Both ADC Channels process data, may be in-phase or out-of-phase by 1/2
DMIC_CLK period depending upon external configuration and timing
Available on either DMIC_0 or DMIC_1
External logic required to support sampling on a single Digital Microphone pin
channel on rising edge and second Digital Microphone right channel on falling
edge of DMIC_CLK for those digital microphones that don’t support alternative
clock edge capability. If both DMIC_0 and DMIC_1 are used to support 2 digital
microphones, 2 separate ADC units will be used, however, this configuration is
not recommended since it consumes two stereo ADC resources.
Requires both DMIC_0 or DMIC_1
External logic required to support sampling on a single Digital Microphone pin
channel on rising edge and second Digital Microphone right channel on falling
edge of DMIC_CLK for those digital microphones that don’t support alternative
clock edge capability. Two ADC units are required to support this configuration
Connected to DMIC_0 and DMIC_1
External logic required to support sampling on a single Digital Microphone pin
channel on rising edge and second Digital Microphone right channel on falling
edge of DMIC_CLK for those digital microphones that don’t support alternative
clock edge capability. Two ADC units are required to support this configuration
1
Single Edge (see Figure 3)
0 or 1
2
Double Edge on either DMIC_0 or
1 (see Figure 4)
OR
Single Edge on DMIC_0 and 1
0 or 1
3
Double Edge on one DMIC pin
and Single Edge on the second
DMIC pin.
0 or 1
4
Double Edge (see Figure 5)
0 or 1
Power
State
DMIC
Widget
Enabled
DMIC_CLK
Output
DMIC_0,1
Notes
D0
Yes
Clock Capable
Input
Capable
Input
Disabled
Input
Disabled
Input
Disabled
Input
Disabled
DMIC_CLK Output is Enabled when either DMIC_0 or DMIC_1 input widget
is enabled. Otherwise, the DMIC_CLK remains low.
DMIC_CLK Output is Enabled when either DMIC_0 or DMIC_1 input widget
is enabled. Otherwise, the DMIC_CLK remains low.
D1
Yes
Clock Disabled
D2
Yes
Clock Disabled
DMIC_CLK remains low
D3
Yes
Clock Disabled
DMIC_CLK remains low
D0-D3
No
Clock Disabled
DMIC_CLK is HIGH-Z with weak pull-down
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 92HD005XX5PRGXYYX8 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:4-CHANNEL HD AUDIO CODEC WITH QUAD DIGITAL MICROPHONE INTERFACE |
| 92HD202 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:8-CHANNEL HIGH DEFINITION AUDIO CODEC |
| 92HD202DX5PRGXYYX | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:8-CHANNEL HIGH DEFINITION AUDIO CODEC |
| 92HD202XX5PRGXYYX | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:8-CHANNEL HIGH DEFINITION AUDIO CODEC |
| 92HD206 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:8-CHANNEL HIGH DEFINITION AUDIO CODEC |
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