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| 型號(hào)： | 91857AG-LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 91857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大?。?/td> | 164K |
| 代理商： | 91857AG-LF |
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2
ICS91857
0494C—08/15/05
Pin Descriptions
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This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels.
ICS91857 is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten differential
pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT, FB_OUTC).The
clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT, FB_INC) the 2.5-
V LVCMOS input (PD#) and the Analog Power input (AVDD).When input (PD#) is low while power is applied, the receivers
are disabled, the PLL is turned off and the differential clock outputs are Tri-Stated. When AVDD is grounded, the PLL
is turned off and bypassed for test purposes.
When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will
enter a low power mode. An input frequency detection circuit on the differential inputs, independent from the input
buffers, will detect the low frequency condition and perform the same low power features as when the (PD#) input
is low. When the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on,
the inputs and outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT,
FB_INC) and the input clock pair (CLK_INC, CLK_INT).
The PLL in the ICS91857 clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT,
FB_INC) provide high-performance, low-skew, low-jitter output differential clocks (CLKT [0:9], CLKC [0:9]). The
ICS91857 is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
ICS91857 is characterized for operation from 0°C to 70°C and will meet JEDEC Standard 82-1 and 82-1A for Registered
DDR Clock Driver.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 91857AGLFT | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 91857AGT | 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Driver Single 60MHz to 230MHz 48-Pin TSSOP T/R |
| 91-858 | 制造商:TE Connectivity 功能描述: |
| 9185954 | 制造商:Molex 功能描述:Conn Unshrouded Header M/F 3 POS 10.06mm Solder ST Thru-Hole |
| 9185B | 功能描述:DC POWER SUPPLY 0-600V, 0.5A / 4 制造商:b&k precision 系列:9180B 零件狀態(tài):在售 類型:工作臺(tái)（AC 至 DC） 電壓 - 電源:115VAC，230VAC 電壓 - 輸出:0 ~ 600VDC 電流 - 輸出:0 ~ 0.5A 顯示類型:LCD 字符數(shù):- 輸出數(shù):1 大小/尺寸:16.339" 長(zhǎng) x 8.268" 寬 x 5.138" 高 （415.00mm x 210.00mm x 130.50mm） 特性:存儲(chǔ)器，可編程，跟蹤，USB 接口 功率（W）:210W 精度 - 電壓表；安培計(jì):0.05% + 100mV; 0.1% + 0.1mA 電壓調(diào)節(jié) - 線路:0.01% + 1mV 電壓調(diào)節(jié) - 負(fù)載:0.01% + 1mV 電流調(diào)節(jié) - 線路:0.01% + 250μA 電流調(diào)節(jié) - 負(fù)載:0.01% + 250μA 紋波:45mV p-p，4.5mV rms 重量:23 磅（10.4kg） 標(biāo)準(zhǔn)包裝:1 |
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