參數(shù)資料
型號(hào)： 9112AM-16LF-T
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 9112 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
封裝： 0.150 INCH, ROHS COMPLIANT, MS-012, SOIC-8
文件頁(yè)數(shù)： 1/8頁(yè)
文件大小： 119K
代理商： 9112AM-16LF-T
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9112A-16
1337K—08/03/07
Block Diagram
Low Skew Output Buffer
Pin Configuration
Zero input - output delay
Frequency range 25 - 133 MHz (3.3V)
High loop filter bandwidth ideal for Spread
Spectrum applications.
Less than 200 ps Jitter between outputs
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 8 pin 150 mil SOIC
or 173 mil TSSOP package.
3.3V ±10% operation
The ICS9112A-16 is a high performance, low skew, low
jitter clock driver.
It uses a phase lock loop (PLL)
technology to align, in both phase and frequency, the REF
input with the CLKOUT signal. It is designed to distribute
high speed clocks in PC systems operating at speeds
from 25 to
133 MHz.
ICS9112A-16 is a zero delay buffer that provides
synchronization between the input and output. The
synchronization is established via CLKOUT feed back to
the input of the PLL. Since the skew between the input and
output is less than +/- 350 pS, the part acts as a zero delay
buffer.
The ICS9112A-16 comes in an eight pin 150 mil SOIC or
173 mil TSSOP package. It has five output clocks. In the
absence of REF input, will be in the power down mode. In
this mode, the PLL is turned off and the output buffers are
pulled low. Power down mode provides the lowest power
consumption for a standby condition.
8 pin SOIC, TSSOP
相關(guān)PDF資料
PDF描述
9112AM-16-T 9112 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
9112AG-16 9112 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
9112AM-16 9112 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
9112AM-16LF 9112 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
9112AG-16LF 9112 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9112AM-16LN 制造商:Integrated Device Technology Inc 功能描述:IDT 9112AM-16LN PHASED LOCKED LOOP (PLL) - Rail/Tube 制造商:Integrated Device Technology Inc 功能描述:IDT 9112AM-16LN Phased Locked Loop (PLL)
9112AM-16T 制造商:INT_CIR_SYS 功能描述:
9112AM-17LF 功能描述:時(shí)鐘緩沖器 PC BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9112AM-17LFT 功能描述:時(shí)鐘緩沖器 PC BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9112AM-26LF 制造商:Integrated Device Technology Inc 功能描述:Clock Fanout Buffer 4-OUT 8-Pin SOIC N Tube 制造商:Integrated Device Technology Inc 功能描述:CLOCK BFFR 4-OUT 8SOIC - Rail/Tube
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