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參數(shù)資料
| 型號(hào)： | 908E621_07 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror |
| 中文描述： | 綜合四半橋和三高的嵌入式微控制器和LIN高端側(cè)鏡 |
| 文件頁(yè)數(shù)： | 50/62頁(yè) |
| 文件大小： | 540K |
| 代理商： | 908E621_07 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
50
908E621
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Analog Die System Trim Values
For improved application performance and to ensure the
outlined datasheet values the analog die needs to be
trimmed. For this purpose 3 trim values are stored in the
Flash memory at address $FDC4 - $FDC6. These values
have to be copied into the analog die SPI registers:
copy $FDC4 into SYSTRIM1 register $0F
copy $FDC5 into SYSTRIM2 register $10
copy $FDC6 into SYSTRIM3 register $11
Note:
This values have to be copied to the respective SPI
register after a reset to ensure proper trimming of the device.
System Test Register (SYSTEST)
The System Test Register is reserved for production
testing and is not allowed to be written to.
System Trim Register 1 (SYSTRIM1)
HVDDT1:0 - HVDD Overcurrent Shutdown Delay Bits
These read/write bits allow to change the filter time (for
capacitive load) for the HVDD over current detection.
Reset clears the HVDDT1:0 bits an sets the delay to the
maximum value.
Table 15. HVDD Overcurrent Shutdown Selection Bits
ITRIM3:0 - IRef Trim Bits
These write only bits are for trimming of the internal
current references IRef (also A0, A0CST). The provided
trim values have to be copied into these bits after every
reset. Reset clears the ITRIM3:0 bits.
Table 16. IRef Trim Bits
System Trim Register 2 (SYSTRIM2)
CRHBHC1:0 - Current Recopy HB1:2 Trim Bits
These write only bits are for trimming of the current
recopy of the half-bridge HB1 and HB2 (CSA=0). The
provided trim values have to be copied into these bits
after every reset. Reset clears the CRHBHC1:0 bits.
Table 17. Current Recopy Trim for HB1:2 (CSA=0)
Register Name and Address: SYSTEST - $0E
Bit7
6
5
4
3
2
1
Bit0
Read
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Write
Reset
0
0
0
0
0
0
0
0
Note: do not write to the reserved bits
Register Name and Address: IBIAS - $0F
Bit7
6
5
4
3
2
1
Bit0
Read
HVDDT1
HVDDT0
0
reserved
0
reserved
ITRIM3
ITRIM2
ITRIM1
ITRIM0
Write
Reset
0
0
0
0
0
0
0
0
Note: do not change (set) the reserved bits
HVDDT1
HVDDT0
typical Delay
0
0
950us
0
1
536us
1
0
234us
1
1
78us
itrim3
itrim2
itrim2
itrim0
Adjustment
0
0
0
0
0
0
0
0
1
2%
0
0
1
0
4%
0
0
1
1
8%
0
1
0
0
12%
0
1
0
1
-2%
0
1
1
0
-4%
0
1
1
1
-8%
1
0
0
0
-12%
Register Name and Address: IFBHBTRIM - $10
Bit7
6
5
4
3
2
1
Bit0
Read
0
0
0
0
0
0
0
0
Write
CRHBHC1
CRHBHC0
CRHB5
CRHB4
CRHB3
CRHB2
CRHB1
CRHB0
Reset
0
0
0
0
0
0
0
0
CRHBHC1
CRHBHC0
Adjustment
0
0
0
0
1
-10%
HVDDT1
HVDDT0
typical Delay
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