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參數(shù)資料
| 型號： | 8XC80C32 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit CMOS (low voltage, low power and high speed) microcontroller families |
| 中文描述： | 8位CMOS（低電壓，低功耗和高速）微控制器系列 |
| 文件頁數(shù)： | 34/55頁 |
| 文件大小： | 361K |
| 代理商： | 8XC80C32 |
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Philips Semiconductors
Preliminary specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
8-bit CMOS (low voltage, low power
and high speed) microcontroller families
1997 Dec 01
208
(8XC51RX+ ONLY)
ERAM
256 BYTES
UPPER
128 BYTES
INTERNAL RAM
LOWER
128 BYTES
INTERNAL RAM
SPECIAL
FUNCTION
REGISTER
ééééé
ééééé
ééééé
ééééé
ééééé
2FF
(RD TO RD+)
FF
00
FF
00
FF
00
80
80
EXTERNAL
DATA
MEMORY
FFFF
0000
0100
300 (RD+ only)
SU00834
Figure 28. Internal and External Data Memory Address Space with EXTRAM = 0
HARDWARE WATCHDOG TIMER (ONE-TIME
ENABLED WITH RESET-OUT FOR 8XC51RX+)
The WDT is intended as a recovery method in situations where the
CPU may be subjected to software upset. The WDT consists of a
14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The
WDT is disabled at reset. To enable the WDT, user must write 01EH
and 0E1H in sequence to the WDTRST, SFR location 0A6H. When
WDT is enabled, it will increment every machine cycle while the
oscillator is running and there is no way to disable the WDT except
through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output reset HIGH pulse at the
RST-pin.
Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to
the WDTRST, SFR location 0A6H. When WDT is enabled, the user
needs to service it by writing to 01EH and 0E1H to WDTRST to
avoid WDT overflow. The 14-bit counter overflows when it reaches
16383 (3FFFH) and this will reset the device. When WDT is
enabled, it will increment every machine cycle while the oscillator is
running. This means the user must reset the WDT at least every
16383 machine cycles. To reset the WDT, the user must write 01EH
and 0E1H to WDTRST. WDTRST is a write only register. The WDT
counter cannot be read or written. When WDT overflows, it will
generate an output RESET pulse at the reset pin. The RESET pulse
duration is 98
×
T
OSC
, where T
OSC
= 1/f
OSC
. To make the best use
of the WDT, it should be serviced in those sections of code that will
periodically be executed within the time required to prevent a WDT
reset.
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