
8XC51SL/LOW VOLTAGE 8XC51SL
Sample WindowD
Begins when the sample capaci-
tor is attached to a selected channel and ends when
the sample capacitor is disconnected from the se-
lected channel.
Successive ApproximationD
An A/D conversion
method which uses a binary search to arrive at the
best digital representation of an analog input.
Temperature CoefficientsD
Change in the stated
variable
per
degree
centrigrade
change. Temperature coefficients are added to the
typical values of a specification to see the effect of
temperature drift.
temperature
Terminal Based CharacteristicD
An actual charac-
teristic which has been rotated and translated to re-
move zero offset and full scale error.
V
CC
RejectionD
Attenuation of noise on the V
CC
line to the A/D converter.
Zero OffsetD
The difference between the expected
and actual input voltage corresponding to the first
code transition.
DATA SHEET REVISION SUMMARY
The following differences exist between this data
sheet
(272271-002)
and
(272271-001).
the
previous
version
1. Data sheet status changed from ‘‘Product Pre-
view’’ to ‘‘Advance Information’’.
2. Title page item number three describing the glob-
al interrupt enable change was removed.
3. Title page item number two was corrected to read
‘‘ . . . was added in configuration register 1.’’
4. In the 8XC51SL DC Characteristics section:
The V
OH
test condition (I
OH
) changed from
b
0.8 mA to
b
60
m
A.
The V
OH1
test condition (I
OH
) changed from
b
4.0 mA to
b
2.0 mA.
V
OH2
was added.
The XTAL1 and EAL pins were added to the I
LI
spec.
The I
TL
spec changed from
b
650
m
A to
b
1 mA.
The I
CC
idle spec changed from 10 mA to 15 mA.
The I
CC
Power Down spec changed from 100
m
A
to TBD.
5. In the Low Voltage 8XC51SL DC Characteristics
section:
The V
OH
spec changed from 2.4V to V
CC
b
0.7
The V
OH
test condition (I
OH
) changed from
b
0.8 mA to
b
60
m
A.
V
OH2
was added.
Pins were clarified in the I
LI
spec.
The I
TL
test condition (V
IN
) was changed from
TBD to 1.5V.
The I
CC
Power Down spec changed from 100
m
A
to 175
m
A.
6. The load capacitance for all timing tables was
changed to 50 pF.
7. In the Host Interface Timing Section TWD
changed from 0 ns to 5 ns.
8. The External Memory Timing table changed as
follows:
Spec.
Old
TLLIV
4TCLCL-50
TPLIV
3TCLCL-50
TPXIZ
TCLCL-15
TAVIV
5TCLCL-50
TRLDV
5TCLCL-50
TLLDV
8TCLCL-50
TAVDV
9TCLCL-50
TMVDV
9TCLCL-50
TMVIV
5TCLCL-50
New
4TCLCL-100
3TCLCL-105
TCLCL-25
5TCLCL-105
5TCLCL-100
8TCLCL-100
9TCLCL-100
Removed
Removed
9. In Figures 5 and 7 the MEMCSL waveforms were
removed.
10. Clarification was added in the Programming Al-
gorithm section.
11. In the A/D Converter Specifications section the
minimum resolution was changed from 256 lev-
els to 255 levels.
12. The Data Sheet Revision Summary was added.
23