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參數(shù)資料
| 型號： | 8xC196KD20 |
| 廠商： | Intel Corp. |
| 英文描述： | COMMERCIAL CHMOS MICROCONTROLLER |
| 中文描述： | 商業(yè)CHMOS單片機 |
| 文件頁數(shù)： | 11/22頁 |
| 文件大小： | 337K |
| 代理商： | 8XC196KD20 |
8XC196KB/8XC196KB16
AC CHARACTERISTICS
(Continued)
Test Conditions: Capacitive load on all pins
e
100 pF, Rise and fall times
e
10 ns, F
OSC
e
12/16 MHz
The 87C196KB will meet these specifications:
Symbol
Description
Min
Max
Units
Notes
F
XTAL
Frequency on XTAL1
12 MHz
3.5
12.0
MHz
(Note 2)
F
XTAL
Frequency on XTAL1
16 MHz
3.5
16.0
MHz
(Note 2)
T
OSC
1/F
XTAL
12 MHz
83.3
286
ns
T
OSC
1/F
XTAL
16 MHz
62.5
286
ns
T
XHCH
XTAL1 High to CLKOUT High or Low
a
20
a
110
ns
T
CLCL
CLKOUT Cycle Time
2 T
OSC
ns
T
CHCL
CLKOUT High Period
T
OSC
b
10
b
10
T
OSC
a
10
a
10
ns
T
CLLH
CLKOUT Falling Edge to ALE Rising
ns
T
LLCH
ALE Falling Edge to CLKOUT Rising
b
15
a
15
ns
T
LHLH
ALE Cycle Time
4 T
OSC
ns
(Note 3)
T
LHLL
ALE High Period
T
OSC
b
10
T
OSC
b
20
T
OSC
b
40
T
OSC
b
35
a
4
T
OSC
a
10
ns
T
AVLL
Address Setup to ALE Falling Edge
ns
T
LLAX
Address Hold after ALE Falling Edge
ns
T
LLRL
ALE Falling Edge to RD Falling Edge
ns
T
RLCL
RD Low to CLKOUT Falling Edge
a
25
ns
T
RLRH
RD Low Period
T
OSC
b
5
T
OSC
a
25
T
OSC
a
25
a
5
ns
(Note 3)
T
RHLH
RD Rising Edge to ALE Rising Edge
T
OSC
ns
(Note 1)
T
RLAZ
RD Low to Address Float
ns
T
LLWL
ALE Falling Edge to WR Falling Edge
T
OSC
b
10
ns
T
CLWL
CLKOUT Low to WR Falling Edge
0
a
25
ns
T
QVWH
Data Stable to WR Rising Edge
T
OSC
b
23
b
5
ns
(Note 3)
T
CHWH
CLKOUT High to WR Rising Edge
a
15
ns
T
WLWH
WR Low Period
T
OSC
b
15
T
OSC
b
15
T
OSC
b
15
T
OSC
b
15
T
OSC
b
10
T
OSC
b
30
T
OSC
b
25
T
OSC
a
5
ns
(Note 3)
T
WHQX
Data Hold after WR Rising Edge
ns
T
WHLH
WR Rising Edge to ALE Rising Edge
T
OSC
a
10
ns
(Note 1)
T
WHBX
BHE, INST HOLD after WR Rising Edge
ns
T
RHBX
BHE, INST HOLD after RD Rising Edge
ns
T
WHAX
AD8–15 hold after WR Rising Edge
ns
T
RHAX
AD8–15 hold after RD Rising Edge
ns
NOTES:
1. Assuming back-to-back bus cycles.
2. Testing performed at 3.5 MHz, however, the device is static by design and will typically operate below 1 Hz.
3. When using wait states, all 2 T
OSC
a
n where n
e
number of wait states.
11
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