參數(shù)資料
型號(hào): 8N3Q001EG-102LCDI8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 3/21頁(yè)
文件大小: 0K
描述: IC CLCK OSC QUAD FREQUENCY 5X7
特色產(chǎn)品: Fourth-generation FemtoClock for VCXO
標(biāo)準(zhǔn)包裝: 1
系列: FemtoClock® NG
類(lèi)型: 時(shí)鐘振蕩器
頻率: 可調(diào)節(jié)/可選擇
電源電壓: 2.375 V ~ 3.465 V
電流 - 電源: 150mA
工作溫度: -40°C ~ 85°C
封裝/外殼: 10-CLCC
包裝: 標(biāo)準(zhǔn)包裝
供應(yīng)商設(shè)備封裝: 10-CLCC
安裝類(lèi)型: 表面貼裝
其它名稱(chēng): 800-2568-6
IDT8N3Q001 REV G Data Sheet
QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A MARCH 6, 2012
11
2012 Integrated Device Technology, Inc.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 1A and 1B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 1A. 3.3V LVPECL Output Termination
Figure 1B. 3.3V LVPECL Output Termination
3.3V
V
CC - 2V
R1
50
Ω
R2
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
+
_
RTT =
* Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
LVPECL
Input
R1
84
Ω
R2
84
Ω
3.3V
R3
125
Ω
R4
125
Ω
Z
o = 50Ω
Z
o = 50Ω
LVPECL
Input
3.3V
+
_
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