參數(shù)資料
型號: 89TTM553
廠商: Integrated Device Technology, Inc.
英文描述: Traffic Manager Co-processor
中文描述: 交通管理協(xié)處理器
文件頁數(shù): 7/30頁
文件大?。?/td> 185K
代理商: 89TTM553
7 of 30
March 3, 2005
IDT 89TTM553
S ignal Name
I/O Type
Dir.
Freq.
Remarks
HT_CLK_CP, HT_CLK_CN
1.5V HSTL Class 1
I
175 MHz
HT QDR SRAMinput clock: This clock pair registers data
inputs on the rising edge of C and C# All synchronous inputs
must meet setup and hold times around the clock rising
edges.
HT_CLK_KP,
HT_CLK_KN
1.5V HSTL Class 1
O
175 MHz
HT QDR SRAM output clock: This clock pair times the control
outputs to the rising edge of K, and times the address and
data outputs to the rising edge of K and K#.
HT_ADDR[19:0]
1.5V HSTL Class 1
O
175 MHz
HT QDR SRAMaddress outputs.
HT_RD_N
1.5V HSTL Class 1
O
175 MHz
HT QDR SRAMsynchronous read output (active low): When
asserted, a read cycle is initiated to the external QDR SRAM
devices.
HT_DIN[35:0]
1.5V HSTL Class 1
I
175 MHz
HT QDR SRAMdata inputs: Input data must meet setup and
hold times around the rising edges of C and C#during read
operations.
HT_WR_N
1.5V HSTL Class 1
O
175 MHz
HT QDR SRAMsynchronous write output (active low): When
asserted, a write cycle is initiated to the external QDR SRAM
devices.
HT_DOUT[35:0]
1.5V HSTL Class 1
O
175 MHz
HT QDR SRAMwrite data outputs: Output data is synchro-
nized to the K and K# during write operations.
HT_VREF[1:0]
0.75V
HSTL reference. Nomnally V
DDQ
/ 2, so connect to 0.75V
Table 6 Head Tail QDR SRAM
S ignal Name
I/O Type
Dir.
Freq.
Remarks
LLT_CLK_CP,
LLT_CLK_CN
1.5V HSTL Class 1
I
175 MHz
LLT QDR SRAMinput clock: This clock pair registers data
inputs on the rising edge of C and C# All synchronous inputs
must meet setup and hold times around the clock rising
edges.
LLT_CLK_KP,
LLT_CLK_KN
1.5V HSTL Class 1
O
175 MHz
LLT QDR SRAMoutput clock: This clock pair times the control
outputs to the rising edge of K, and times the address and
data outputs to the rising edge of K and K#.
LLT_ADDR[19:0]
1.5V HSTL Class 1
O
175 MHz
LLT QDR SRAMaddress outputs.
LLT_RD_N
1.5V HSTL Class 1
O
175 MHz
LLT QDR SRAMsynchronous read output (active low): When
asserted, a read cycle is initiated to the external QDR SRAM
devices.
LLT_DIN[10:0]
1.5V HSTL Class 1
I
175 MHz
LLT QDR SRAM data inputs: Input data must meet setup and
hold times around the rising edges of C and C#during read
operations.
LLT_WR_N
1.5V HSTL Class 1
O
175 MHz
LLT QDR SRAMsynchronous write output (active low): When
asserted, a write cycle is initiated to the external QDR SRAM
devices.
LLT_DOUT[10:0]
1.5V HSTL Class 1
O
175 MHz
LLT QDR SRAMwrite data outputs: Output data is synchro-
nized to the K and K# during write operations.
Table 7 Linked List Table QDR SRAM
相關(guān)PDF資料
PDF描述
89TTM553BL Traffic Manager Co-processor
8A05 CURRENT 8.0 Amperes VOLTAGE 50 TO 100 VOLTS
8A10 CURRENT 8.0 Amperes VOLTAGE 50 TO 100 VOLTS
8A100 CURRENT 8.0 Amperes VOLTAGE 50 TO 100 VOLTS
8A20 CURRENT 8.0 Amperes VOLTAGE 50 TO 100 VOLTS
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