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參數(shù)資料
| 型號(hào)： | 89TTM552BL |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Traffic Manager Co-processor |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA960 |
| 封裝： | 35 X 35 MM, 1 MM PITCH, FPBGA-960 |
| 文件頁數(shù)： | 7/30頁 |
| 文件大?。?/td> | 185K |
| 代理商： | 89TTM552BL |
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March 3, 2005
IDT 89TTM553
S ignal Name
I/O Type
Dir.
Freq.
Remarks
HT_CLK_CP, HT_CLK_CN
1.5V HSTL Class 1
I
175 MHz
HT QDR SRAMinput clock: This clock pair registers data
inputs on the rising edge of C and C# All synchronous inputs
must meet setup and hold times around the clock rising
edges.
HT_CLK_KP,
HT_CLK_KN
1.5V HSTL Class 1
O
175 MHz
HT QDR SRAM output clock: This clock pair times the control
outputs to the rising edge of K, and times the address and
data outputs to the rising edge of K and K#.
HT_ADDR[19:0]
1.5V HSTL Class 1
O
175 MHz
HT QDR SRAMaddress outputs.
HT_RD_N
1.5V HSTL Class 1
O
175 MHz
HT QDR SRAMsynchronous read output (active low): When
asserted, a read cycle is initiated to the external QDR SRAM
devices.
HT_DIN[35:0]
1.5V HSTL Class 1
I
175 MHz
HT QDR SRAMdata inputs: Input data must meet setup and
hold times around the rising edges of C and C#during read
operations.
HT_WR_N
1.5V HSTL Class 1
O
175 MHz
HT QDR SRAMsynchronous write output (active low): When
asserted, a write cycle is initiated to the external QDR SRAM
devices.
HT_DOUT[35:0]
1.5V HSTL Class 1
O
175 MHz
HT QDR SRAMwrite data outputs: Output data is synchro-
nized to the K and K# during write operations.
HT_VREF[1:0]
0.75V
—
—
HSTL reference. Nomnally V
DDQ
/ 2, so connect to 0.75V
Table 6 Head Tail QDR SRAM
S ignal Name
I/O Type
Dir.
Freq.
Remarks
LLT_CLK_CP,
LLT_CLK_CN
1.5V HSTL Class 1
I
175 MHz
LLT QDR SRAMinput clock: This clock pair registers data
inputs on the rising edge of C and C# All synchronous inputs
must meet setup and hold times around the clock rising
edges.
LLT_CLK_KP,
LLT_CLK_KN
1.5V HSTL Class 1
O
175 MHz
LLT QDR SRAMoutput clock: This clock pair times the control
outputs to the rising edge of K, and times the address and
data outputs to the rising edge of K and K#.
LLT_ADDR[19:0]
1.5V HSTL Class 1
O
175 MHz
LLT QDR SRAMaddress outputs.
LLT_RD_N
1.5V HSTL Class 1
O
175 MHz
LLT QDR SRAMsynchronous read output (active low): When
asserted, a read cycle is initiated to the external QDR SRAM
devices.
LLT_DIN[10:0]
1.5V HSTL Class 1
I
175 MHz
LLT QDR SRAM data inputs: Input data must meet setup and
hold times around the rising edges of C and C#during read
operations.
LLT_WR_N
1.5V HSTL Class 1
O
175 MHz
LLT QDR SRAMsynchronous write output (active low): When
asserted, a write cycle is initiated to the external QDR SRAM
devices.
LLT_DOUT[10:0]
1.5V HSTL Class 1
O
175 MHz
LLT QDR SRAMwrite data outputs: Output data is synchro-
nized to the K and K# during write operations.
Table 7 Linked List Table QDR SRAM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 89TTM553 | Traffic Manager Co-processor |
| 89TTM553BL | Traffic Manager Co-processor |
| 8A05 | CURRENT 8.0 Amperes VOLTAGE 50 TO 100 VOLTS |
| 8A10 | CURRENT 8.0 Amperes VOLTAGE 50 TO 100 VOLTS |
| 8A100 | CURRENT 8.0 Amperes VOLTAGE 50 TO 100 VOLTS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 89TTM553 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Traffic Manager Co-processor |
| 89TTM553BL | 制造商:Integrated Device Technology Inc 功能描述:89TTM553BL, ATM TRAFFIC MANAGEMENT 10GBPS 1.8V 960-PIN FCBGA - Trays 制造商:Integrated Device Technology Inc 功能描述:IDT 89TTM553BL, ATM Traffic Management 10Gbps 1.8V 960-Pin FCBGA |
| 89U150368TT-0080 | 制造商:MISCELLANEOUS 功能描述: |
| 89-WHITE-1"X60YD | 功能描述:TAPE ELECTRICAL GLASS CLOTH 1" RoHS:是 類別:膠帶，粘合劑 >> 帶 系列:89 MSDS 材料安全數(shù)據(jù)表:42x, 43x, 140x, 141x, 1449, 1450, 433,438,33xx MSDS 標(biāo)準(zhǔn)包裝:1 系列:425 膠帶類型:鋁箔 膠合劑:丙烯酸 背襯，載體:鋁，極軟的 厚度:0.0046"（4.6 mils，0.117mm） 厚度 - 膠合劑:0.0016"（1.6 mils，0.041mm） 厚度 - 背膠，載體，襯墊:0.0028"（2.8 mils，0.071mm） 寬:2.00"（50.80mm） 長(zhǎng)度:15'（4.6m）5 碼 顏色:銀 使用:熱耗散，反射 溫度范圍:-65 ~ 300°F（-54 ~ 149°C） 包裝:散裝 工具箱:3M10454-ND - MRO TAPE KIT - PREMIUM3M10451-ND - MRO TAPE KIT - STANDARDTK3434-ND - HOME TAPE KIT - PREMIUM3M10395-ND - DESIGN ENGR SOLUTION SEMINAR KIT3M10394-ND - DESIGN ENGR METAL FOIL TAPE KIT 其它名稱:3M9778 |
| 89WHR10 | 制造商:TT Electronics / BI Technologies 功能描述:Res Cermet Trimmer 10 Ohm 20% 0.75W(3/4W) 20(Elec)Turn 2.36mm (20.57 X 4.83 X 8.64mm) Pin Thru-Hole Box |
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