參數(shù)資料
型號: 89HPES4T4
廠商: Integrated Device Technology, Inc.
英文描述: 4-Lane 4-Port PCI Express Switch
中文描述: 4巷4端口的PCI Express開關(guān)
文件頁數(shù): 1/23頁
文件大?。?/td> 243K
代理商: 89HPES4T4
1 of 23
September 7, 2007
2007 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
A
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
Devic e Overview
The 89HPES4T4 is a member of IDT’s PRECISE famly of PCI
Express switching solutions. The PES4T4 is a 4-lane, 4-port peripheral
chip that performs PCI Express Base switching. It provides connectivity
and switching functions between a PCI Express upstreamport and up to
four downstreamports and supports switching between downstream
ports.
Features
High Performance PCI Express Switch
– Four 2.5 Gbps PCI Express lanes
– Four switch ports
– x1 Upstreamport
– Three x1 Downstreamports
– Low latency cut-through switch architecture
– Support for Max payload sizes up to 256 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration fromserial EEPROM
Legacy Support
– PCI compatible INTx emulation
– Bus locking
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates four 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC and Advanced Error Reporting
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC mother-
boards
Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Supports PCI Power Management Interface specification (PCI-
PM1.2)
– Unused SerDes are disabled.
– Supports Advanced Configuration and Power Interface Speci-
fication, Revision 2.0 (ACPI) supporting active link state
Testability and Debug Features
– Built in Pseudo-RandomBit Stream(PRBS) generator
– Numerous SerDes test modes
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Block Diagram
Figure 1 Internal Block Diagram
4-Port Switch Core / 4 PCI Express Lanes
Frame Buffer
Route Table
Port
Arbitration
Scheduler
SerDes
Phy
Logical
Layer
Mux / Demux
Transaction Layer
Data Link Layer
(Port 0)
(Port 2)
SerDes
Phy
Logical
Layer
Mux / Demux
Transaction Layer
Data Link Layer
SerDes
Phy
Logical
Layer
Mux / Demux
Transaction Layer
Data Link Layer
(Port 3)
(Port 4)
SerDes
Phy
Logical
Layer
Transaction Layer
Data Link Layer
Mux / Demux
89HPES4T4
Data Sheet
Advance Information*
4-Lane 4-Port
PCI Express Switch
相關(guān)PDF資料
PDF描述
89HPES4T4ZABC 4-Lane 4-Port PCI Express Switch
89HPES4T4ZABCG 4-Lane 4-Port PCI Express Switch
89HPES5T5ZABC 5-Lane 5-Port PCI Express Switch
89HPES5T5ZABCG 5-Lane 5-Port PCI Express Switch
89PES5T5 5-Lane 5-Port PCI Express Switch
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