
1 of 2
February 8, 2007
2007 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
Devic e Overview
The 89HPES16T7 is a member of the IDT PRECISE famly of PCI
Express switching solutions. The PES16T7 is a 16-lane, 7-port periph-
eral chip that performs PCI Express Packet switching with a feature set
optimzed for high performance applications such as servers, storage
and communications/networking. It provides connectivity and switching
functions between a PCI Express upstreamport and up to seven down-
streamports and supports switching between downstreamports.
Features
High Performance PCI Express Switch
– Sixteen 2.5 Gbps PCI Express lanes
– Seven switch ports
– Upstreamport configurable up to x8
– Two downstreamports configurable up to x4, four downstream
ports are x1
– Low-latency cut-through switch architecture
– Support for Max Payload Sizes up to 2048 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
◆
Flexible Architecture with Numerous Configuration Options
– Automatic per port link width negotiation to x8, x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration fromserial EEPROM
◆
Legacy Support
– PCI compatible INTx emulation
– Bus locking
◆
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates sixteen 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
◆
Reliability, Availability, and Serviceability (RAS) Features
– Supports ECRC and Advanced Error Reporting
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC and
server motherboards
◆
Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Supports PCI Power Management Interface specification (PCI-
PM1.1)
Supports device power management states: D0, D3
hot
and
D3
cold
– Unused SerDes are disabled
Block Diagram
Figure 1 Internal Block Diagram
7-Port Switch Core / 16 PCI Express Lanes
Frame Buffer
Route Table
Port
Arbitration
Scheduler
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
Phy
Logical
Layer
(Port 0)
(Port 1)
(Port 3)
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
Phy
Logical
Layer
(Port 2)
SerDes
Phy
Logical
Layer
(Port 6)
TL
DLL
Mux/Demux
SerDes
Phy
Logical
Layer
TL
DLL
Mux/Demux
89HPES16T7
Product Brief
16-Lane 7-Port
PCI Express Switch