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參數(shù)資料
| 型號： | 89C54 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash |
| 中文描述： | 80C51的8位單片機(jī)系列4K/8K/16K/32K閃光 |
| 文件頁數(shù)： | 19/32頁 |
| 文件大?。?/td> | 212K |
| 代理商： | 89C54 |
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Philips Semiconductors
Product specification
89C51/89C52/89C54/89C58
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
1999 Oct 27
19
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the
ALE output.
Reduced EMI Mode
AUXR (8EH)
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
AO
AUXR.0
AO
Turns off ALE output.
Dual DPTR
The dual DPTR structure (see Figure 13) is a way by which the chip
will specify the address of an external data memory location. There
are two 16-bit DPTR registers that address the external memory,
and a single bit called DPS = AUXR1/bit0 that allows the program
code to switch between them.
New Register Name: AUXR1#
SFR Address: A2H
Reset Value: xxxx00x0B
AUXR1 (A2H)
7
6
5
4
3
2
1
0
–
–
–
–
GF2
0
–
DPS
Where:
DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.
Select Reg
DPS
DPTR0
DPTR1
0
1
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
The GF0 bit is a general purpose user-defined flag. Note that bit 2 is
not writable and is always read as a zero. This allows the DPS bit to
be quickly toggled simply by executing an INC AUXR1 instruction
without affecting the GF2 bit.
DPS
DPTR1
DPTR0
DPH
(83H)
DPL
(82H)
EXTERNAL
DATA
MEMORY
SU00745A
BIT0
AUXR1
Figure 13.
DPTR Instructions
The instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:
INC DPTR
Increments the data pointer by 1
MOV DPTR, #data16
Loads the DPTR with a 16-bit constant
MOV A, @ A+DPTR
Move code byte relative to DPTR to ACC
MOVX A, @ DPTR
Move external RAM (16-bit address) to
ACC
MOVX @ DPTR , A
Move ACC to external RAM (16-bit
address)
JMP @ A + DPTR
Jump indirect relative to DPTR
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See application note AN458 for more details.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 89C51 | 80C51 8-bit microcontroller family 4K Flash(80C51八位微控制器系列 4K 閃速存儲器) |
| 89C52 | 80C51 8-bit microcontroller family8KFlash(80C51八位微控制器系列 8K閃速存儲器) |
| 89C58 | 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash |
| 89CNQ135 | |
| 89CNQ150 | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 89C55 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-Bit Microcontroller with 20K Bytes Flash |
| 89C58 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 4K/8K/16K/32K Flash |
| 89C59 | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| 89C61X2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit Flash microcontroller family |
| 89C664HFA | 制造商: 功能描述: 制造商:undefined 功能描述: |
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