參數(shù)資料
型號(hào): 89C538
廠商: NXP Semiconductors N.V.
英文描述: CMOS single-chip 8-bit microcontrollers with FLASH program memory
中文描述: CMOS單芯片8位微控制器的FLASH程序存儲(chǔ)器
文件頁(yè)數(shù): 17/35頁(yè)
文件大小: 221K
代理商: 89C538
Philips Semiconductors
Preliminary specification
89C535/89C536/89C538
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
1997 Jun 05
17
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0
°
C to +70
°
C; 5V
±
10%; V
SS
= 0V
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
CONDITIONS
MIN
–0.5
MAX
V
IL
V
IH
V
IH1
Input low voltage
4.5V < V
CC
< 5.5V
0.2V
CC
–0.1
V
CC
+0.5
V
CC
+0.5
V
Input high voltage (ports 0, 1, 2, 3, EA)
0.2V
CC
+0.9
0.7V
CC
V
Input high voltage, XTAL1, RST
V
V
OL
Output low voltage, ports 1, 2, 3
6
V
CC
= 4.5V
I
OL
1
V
CC
= 4.5V
I
OL
1
V
CC
= 4.5V
I
OH
= –30
μ
A
V
CC
= 4.5V
I
OH
μ
A
V
IN
= 0.4V
V
IN
= 2.0V
See note 3
0.45 < V
IN
< V
CC
– 0.3
See note 4
V
CC
= 5.5V
FREQ = 24 MHz
T
amb
= 0
°
C to 70
°
C
0.4
V
V
OL1
Output low voltage, port 0, ALE, PSEN
5, 6
0.4
V
V
OH
Output high voltage, ports 1, 2, 3
2
V
CC
– 0.7
V
V
OH1
Output high voltage (port 0 in external bus mode), ALE
7
,
PSEN
2
Logical 0 input current, ports 1, 2, 3
V
CC
– 0.7
V
I
IL
–1
–50
μ
A
I
TL
Logical 1-to-0 transition current, ports 1, 2, 3
–650
μ
A
I
LI
I
CC
Input leakage current, port 0
±
10
μ
A
Power supply current (see Figure 16):
Active mode
Idle mode
Power-down mode or clock stopped
(see Figure 20 for conditions)
60
25
100
mA
mA
μ
A
R
RST
NOTES:
1. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
OL
s of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
OL
can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
2. Capacitive loading on ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the V
CC
–0.7 specification when the
address bits are stabilizing.
3. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V
is approximately 2V.
4. See Figures 17 through 20 for I
test conditions.
Active mode:
I
CC(MAX)
= 0.9
×
FREQ. + 1.1mA
Idle mode:
I
CC(MAX)
= 0.18
×
FREQ. +1.0mA; See Figure 16.
5. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
6. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin:
15mA
Maximum I
OL
per 8-bit port:
26mA
Maximum total I
OL
for all outputs:
71mA
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
7. ALE is tested to V
OH1
, except when ALE is off then V
OH
is the voltage specification.
8. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF
(except EA is 25pF).
Internal reset pull-down resistor
40
225
k
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