參數(shù)資料
型號(hào): 88C39L-AF5-R
廠商: 友順科技股份有限公司
英文描述: BUILT-IN DELAY CIRCUIT HIGH-PRECISION VOLTAGE DETECTOR
中文描述: 內(nèi)置延遲電路高精度電壓檢測器
文件頁數(shù): 7/16頁
文件大?。?/td> 227K
代理商: 88C39L-AF5-R
88CXX
CMOS IC
UNISONIC TECHNOLOGIES CO., LTD
7
www.unisonic.com.tw
QW-R502-040,A
T ECHNICAL T ERMS
1. Detection voltage (-V
DET
)
The detection voltage -V
DET
is the voltage at which the output switches to low. This detection voltage varies
slightly among products of the same type. The variation of voltages between the specified minimum [(-V
DET
)min.]
and maximum [(-V
DET
)max.] values is called the detection voltage range (See Figure 1).
Example: For the -V
DET
=1.5V, detection voltage lies in the range of 1.470
is 1.470 in a product while -V
DET
is 1.530 in another of the same -V
DET
=1.5V.
(-V
DET
)
1.530. This means that -V
DET
2. Release voltage (+V
DET
)
The release voltage +V
DET
is the voltage at which the output returns (is “released”) to high. This release voltage
varies slightly among products of the same type. The variation of voltages between the specified minimum
[(+V
DET
)min.] and maximum [(+V
DET
)max.] values is called the release voltage range (See Figure 2).
Example: For the -V
DET
=1.5V, the release voltage lies in the range of 1.514
+V
DET
is 1.514 in a product while +V
DET
is 1.652 in another of the same -V
DET
=1.5V.
(+V
DET
)
1.652. This means that
Remark: Although the detection voltage and release voltage overlap in the range of 1.514 V ~ 1.530 V, +V
DET
will always be larger than -V
DET
.
OUT
(-V
DET
)Max.
(-V
DET
)Min.
Detection voltage
Voltage range Detection
OUT
(+V
DET
) Max.
(+V
DET
) Min.
Release voltage
Release voltage range
V
DD
V
D
Figure 1
Figure 2 (C
D
=0
F
)
3. Hysteresis width (V
HYS
)
The hysteresis width is the voltage difference between the detection voltage and the release voltage (B-A=V
HYS
in
Figure 7). By giving a device hysteresis, trouble such as noise at the input is avoided.
4. Delay time (t
d
)
The delay time is a time that the input voltage to V
DD
terminal exceeds the release voltage (+V
DET
) and then the
output of the OUT terminal inverts. The delay time can be changed by the additional external capacitor C
D
.
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