參數(shù)資料
型號(hào)： 87C52X2
廠商： NXP Semiconductors N.V.
英文描述： 80C51 8-bit microcontroller family 4K/8K/16K/32K ROM/OTP 128B/256B RAM low voltage 2.7 to 5.5 V, low power, high speed 30/33 MHz
中文描述： 80C51的8位單片機(jī)系列4K/8K/16K/32K的ROM / RAM的檢察官辦公室128B/256B低電壓2.7至5.5 V，低功耗，高速33分之30兆赫
文件頁(yè)數(shù)： 31/62頁(yè)
文件大小： 403K
代理商： 87C52X2
Philips Semiconductors
Product data
P80C3xX2; P80C5xX2;
P87C5xX2
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
2003 Jan 24
31
SCON
Address = 98H
Reset Value = 0000 0000B
SM0/FE
SM1
SM2
REN
TB8
RB8
Tl
Rl
Bit Addressable
(SMOD0 = 0/1)*
Symbol
Position
Function
FE
SCON.7
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not
cleared by valid frames but should be cleared by software. The SMOD0 bit must be set to enable
access to the FE bit.*
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
Serial Port Mode Bit 1
SM0
SM1
SCON.7
SCON.6
SM2
SCON.5
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set
unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or
Broadcast Address. In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was
received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0.
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that
was received.
In Mode 0, RB8 is not used.
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of
the stop bit in the other modes, in any serial transmission. Must be cleared by software.
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the
stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by
software.
REN
TB8
RB8
SCON.4
SCON.3
SCON.2
Tl
SCON.1
Rl
SCON.0
NOTES:
*SMOD0 is located at PCON.6.
**f
OSC
= oscillator frequency
SU01628
7
6
5
4
3
2
1
0
SM0
0
0
1
SM1
0
1
0
Mode
0
1
2
Description
shift register
8-bit UART
9-bit UART
Baud Rate**
f
OSC
/12 (12-clk mode) or f
OSC
/6 (6-clk mode)
variable
f
OSC
/64 or f
OSC
/32 or f
OSC
/16 (6-clock mode) or
f
OSC
/32 (12-clock mode)
variable
1
1
3
9-bit UART
Figure 18. SCON: Serial Port Control Register
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