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參數(shù)資料
| 型號(hào)： | 87C453 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O |
| 中文描述： | 80C51的8位單片機(jī)系列8K/256檢察官辦公室/光盤，擴(kuò)展的I / O |
| 文件頁(yè)數(shù)： | 15/26頁(yè) |
| 文件大小： | 188K |
| 代理商： | 87C453 |
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Philips Semiconductors
Preliminary specification
83C453/87C453
80C51 8-bit microcontroller family
8K/256 OTP/ROM, expanded I/O
1998 Apr 23
15
AC ELECTRICAL CHARACTERISTICS
T
amb
= 0
°
C to +70
°
C, V
CC
= 5V
±
10%, V
SS
= 0V
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/t
CLCL
Oscillator frequency
3.5
16
MHz
t
LHLL
9
ALE pulse width
85
2t
CLCL
–40
ns
t
AVLL
9
Address valid to ALE low
22
t
CLCL
–40
ns
t
LLAX
9
Address hold after ALE low
32
t
CLCL
–30
ns
t
LLIV
9
ALE low to valid instruction in
150
4t
CLCL
–100
ns
t
LLPL
9
ALE low to PSEN low
32
t
CLCL
–30
ns
t
PLPH
9
PSEN pulse width
142
3t
CLCL
–45
ns
t
PLIV
9
PSEN low to valid instruction in
82
3t
CLCL
–105
ns
t
PXIX
9
Input instruction hold after PSEN
0
0
ns
t
PXIZ
9
Input instruction float after PSEN
37
t
CLCL
–25
ns
t
AVIV
9
Address to valid instruction in
207
5t
CLCL
–105
ns
t
PLAZ
9
PSEN low to address float
10
10
ns
Data Memory
t
RLRH
10, 11
RD pulse width
275
6t
CLCL
–100
ns
t
WLWH
10, 11
WR pulse width
275
6t
CLCL
–100
ns
t
RLDV
10, 11
RD low to valid data in
147
5t
CLCL
–165
ns
t
RHDX
10, 11
Data hold after RD
0
0
ns
t
RHDZ
10, 11
Data float after RD
65
2t
CLCL
–60
ns
t
LLDV
10, 11
ALE low to valid data in
350
8t
CLCL
–150
ns
t
AVDV
10, 11
Address to valid data in
397
9t
CLCL
–165
ns
t
LLWL
10, 11
ALE low to RD or WR low
137
239
3t
CLCL
–50
3t
CLCL
+50
ns
t
AVWL
10, 11
Address valid to WR low or RD low
122
4t
CLCL
–130
ns
t
QVWX
10, 11
Data valid to WR transition
13
t
CLCL
–50
ns
t
WHQX
10, 11
Data hold after WR
13
t
CLCL
–50
ns
t
RLAZ
10, 11
RD low to address float
0
0
ns
t
WHLH
10, 11
RD or WR high to ALE high
23
103
t
CLCL
–40
t
CLCL
+40
ns
Shift Register
t
XLXL
12
Serial port clock cycle time
750
12t
CLCL
ns
t
QVXH
12
Output data setup to clock rising edge
492
10t
CLCL
–133
ns
t
XHQX
12
Output data hold after clock rising edge
8
2t
CLCL
–117
ns
t
XHDX
12
Input data hold after clock rising edge
0
0
ns
t
XHDV
12
Clock rising edge to input data valid
492
10t
CLCL
–133
ns
Port 6 input (input rise and fall times = 5ns)
t
FLFH
15
PE width
209
3t
CLCL
+20
ns
t
ILIH
15
IDS width
209
3t
CLCL
+20
ns
t
DVIH
15
Data setup to IDS high or PE high
0
0
ns
t
IHDZ
15
Data hold after IDS high or PE high
30
30
ns
t
IVFV
16
IDS to BFLAG (IBF) delay
130
130
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 87C51 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CMOS single-chip 8-bit microcontrollers |
| 87C51/BQA | 制造商:Rochester Electronics LLC 功能描述: |
| 87C51/BUA | 制造商:Rochester Electronics LLC 功能描述: |
| 87C51-16/BUA | 制造商:Rochester Electronics LLC 功能描述: |
| 87C51F | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER |
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