參數(shù)資料
型號： 87C38X2
廠商： NXP Semiconductors N.V.
英文描述： RECTIFIER BRIDGE 4A 400V 120A-ifsm 1V-vf 5uA-ir KBJ 20/TUBE
中文描述： 80C51的8位單片機系列4K/8K/16K/32K的ROM / RAM的檢察官辦公室128B/256B低電壓2.7至5.5 V，低功耗，高速33分之30兆赫
文件頁數(shù)： 42/62頁
文件大?。?/td> 403K
代理商： 87C38X2
Philips Semiconductors
Product data
P80C3xX2; P80C5xX2;
P87C5xX2
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
2003 Jan 24
42
AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE, 5 V
±
10% OPERATION)
T
amb
= 0
°
C to +70
°
C or –40
°
C to +85
°
C ; V
CC
= 5 V
±
10%, V
SS
= 0 V
1,2,3,4,5
Symbol
Figure
Parameter
Limits
MIN
16 MHz Clock
MIN
Unit
MAX
MAX
1/t
CLCL
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
Data Memory
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
WHQX
t
QVWH
t
RLAZ
t
WHLH
External Clock
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Shift register
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
31
27
27
27
27
27
27
27
27
27
27
27
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
0
t
CLCL
–8
0.5 t
CLCL
–13
0.5 t
CLCL
–20
–
0.5 t
CLCL
–10
1.5 t
CLCL
–10
–
0
–
–
–
30
–
–
–
2 t
CLCL
–35
–
–
1.5 t
CLCL
–35
–
0.5 t
CLCL
–10
2.5 t
CLCL
–35
10
–
54.5
18.25
11.25
–
21.25
83.75
–
0
–
–
–
–
–
–
–
90
–
–
58.75
–
21.25
121.25
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
28
29
28
28
28
28
28
28, 29
28, 29
29
29
29
28
28, 29
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
3 t
CLCL
–20
3 t
CLCL
–20
–
0
–
–
–
1.5 t
CLCL
–15
2 t
CLCL
–15
0.5 t
CLCL
–25
0.5 t
CLCL
–15
3.5 t
CLCL
–5
–
0.5 t
CLCL
–10
–
–
2.5 t
CLCL
–35
–
t
CLCL
–10
4 t
CLCL
–35
4.5 t
CLCL
–35
1.5 t
CLCL
+15
–
–
–
–
0
0.5 t
CLCL
+10
167.5
167.5
–
0
–
–
–
78.75
110
6.25
16.25
213.75
–
21.25
–
–
121.25
–
52.5
215
246.25
108.75
–
–
–
–
0
41.25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
31
31
31
31
High time
Low time
Rise time
Fall time
0.4 t
CLCL
0.4 t
CLCL
–
–
t
CLCL
– t
CLCX
t
CLCL
– t
CHCX
5
5
–
–
–
–
–
–
–
–
ns
ns
ns
ns
30
30
30
30
30
Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
6 t
CLCL
5 t
CLCL
–25
t
CLCL
–15
0
–
–
–
–
–
5 t
CLCL
–133
375
287.5
47.5
0
–
–
–
–
–
179.5
ns
ns
ns
ns
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN=100 pF, load capacitance for all outputs = 80 pF
3. Interfacing the microcontroller to devices with float time up to 45ns is permitted. This limited bus contention will not cause damage to port 0
drivers.
4. Parts are guaranteed by design to operate down to 0 Hz.
5. Data shown in the table are the best mathematical models for the set of measured values obtained in tests. If a particular parameter
calculated at a customer specified frequency has a negative value, it should be considered equal to zero.
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