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| 型號(hào)： | 87C151 |
| 廠商： | Intel Corp. |
| 英文描述： | Low Voltage, Low Power, 16-/24-Bit, Dual Sigma Delta ADC; Package: TSSOP; No of Pins: 28; Temperature Range: Industrial |
| 中文描述： | 高性能CHMOS單片機(jī) |
| 文件頁(yè)數(shù)： | 16/33頁(yè) |
| 文件大?。?/td> | 297K |
| 代理商： | 87C151 |
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8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
AC Characteristics
Table
8XC151SA/SB with no wait states. External wait
states can be added by extending PSEN
Y
/RD
Y
/
WR
Y
and/or by extending ALE. In the table, Notes
3 and 5 mark parameters affected by an ALE wait
8
lists
AC
timing
parameters
for
the
state, and Notes 4 and 5 mark parameters affected
by a PSEN
Y
/RD
Y
/WR
Y
wait state.
Figures 5–11 show the bus cycles with the timing
parameters.
Table 9. AC Characteristics (Capacitive Loading
e
50 pF)
Symbol
Parameter
@
Max F
OSC
(1)
F
OSC
Variable
Units
Min
Max
Min
Max
F
OSC
XTAL1 Frequency
N/A
N/A
0
16
MHz
T
OSC
1/F
OSC
N/A
N/A
ns
@
12 MHz
@
16 MHz
83.3
62.5
T
LHLL
ALE Pulse Width
@
12 MHz
@
16 MHz
ns
(3)
68.3
47.5
(1
a
2M)
T
OSC
b
15
T
AVLL
Address Valid to ALE Low
@
12 MHz
@
16 MHz
ns
(3)
58.3
37.5
(1
a
2M)
T
OSC
b
25
T
LLAX
Address Hold after ALE Low
@
12 MHz
@
16 MHz
ns
10
10
10
T
RLRH
(2)
RD
Y
or PSEN
Y
Pulse Width
@
12 MHz
@
16 MHz
ns
(4)
151.6
110
2(1
a
N)
T
OSC
b
15
T
WLWH
WR
Y
Pulse Width
@
12 MHz
@
16 MHz
ns
(4)
151.6
110
2(1
a
N)
T
OSC
b
15
T
LLRL
(2)
ALE Low to RD
Y
or PSEN
Y
Low
@
12 MHz
@
16 MHz
ns
58.3
37.5
Tosc
b
25
T
LHAX
ALE High to Address Hold
@
12 MHz
@
16 MHz
ns
(3)
83.3
62.5
(1
a
2M)
T
OSC
NOTES:
1. 16 MHz.
2. Specifications for PSEN
Y
are identical to those for RD
Y
.
3. In the formula, M
e
Number of wait states (0 or 1) for ALE.
4. In the formula, N
e
Number of wait states (0, 1, 2, or 3) for RD
Y
/PSEN
Y
/WR
Y
.
5. ‘‘Typical’’ specifications are untested and not guaranteed.
16
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