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參數(shù)資料
| 型號(hào)： | 87C055 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Microcontrollers for TV and video MTV |
| 中文描述： | 電視和視頻微控制器MTV |
| 文件頁(yè)數(shù)： | 29/40頁(yè) |
| 文件大?。?/td> | 243K |
| 代理商： | 87C055 |
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1996 Mar 22
29
Philips Semiconductors
Product specification
Microcontrollers for TV and video (MTV)
83C145; 83C845
83C055; 87C055
14.5
V
DD
= 5 V
±
10%; V
SS
= 0 V; T
amb
= 21 to 27
°
C.
EPROM Programming and Verification
Note
1.
Address should be valid at least 24t
CLCL
before the rising edge of P0.0 (V
PP
).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
1/t
CLCL
t
AVGL(1)
t
GHAX
t
DVGL
t
GHDX
t
SHGL
t
GHSL
t
GLGH
t
AVQV(1)
t
GHGL
t
SYNL
t
SYNH
t
MASEL
t
HAHLD
t
HASET
t
ADSTA
Oscillator/clock frequency
Address setup to P0.1 (PROG) LOW
Address hold after P0.1 (PROG) HIGH
Data setup to P0.1 (PROG) LOW
Data hold after P0.1 (PROG) HIGH
V
PP
setup to P0.1 (PROG) LOW
V
PP
hold after P0.1 (PROG) HIGH
P0.1 (PROG) width
V
PP
(V
DD
) LOW to data valid
P0.1 (PROG) HIGH to P0.1 (PROG) LOW
P0.0 (sync pulse) LOW
P0.0 (sync pulse) HIGH
ASEL HIGH time
Address hold time
Address setup to ASEL
Low address to address stable
1.2
6
MHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
10 + 24t
CLCL
48t
CLCL
38t
CLCL
36t
CLCL
10
10
90
10
4t
CLCL
8t
CLCL
13t
CLCL
2t
CLCL
13t
CLCL
13t
CLCL
110
48t
CLCL
Fig.11 Program/Verify cycle.
handbook, full pagewidth
tMASEL
tHASET
tHAHLD
tAVQV
tGHDX
tDVGL
tADSTA
tGLGH
tGHGL
tGHSL
tSHGL
P0.0 [V (p-p)]
P0.1 (PROG)
P0.2 (ASEL)
PORT 2
PORT 3
5 V
12.75 V
5 V
98
μ
s MIN
10
μ
s MIN
25 PULSES
HIGH ADDRESS
LOW ADDRESS
INVALID DATA
VALID DATA
VALID DATA
INVALID DATA
DATA TO BE
PROGRAMMED
verify mode
verify mode
program mode
MBE769
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