參數(shù)資料
型號: 874003DG-02T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 874003 SERIES, PLL BASED CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封裝: 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20
文件頁數(shù): 12/14頁
文件大?。?/td> 1050K
代理商: 874003DG-02T
IDT / ICS PCI EXPRESS JITTER ATTENUATOR
7
ICS874003AG-02 REV A March 3, 2009
ICS874003-02
PCI EXPRESS JITTER ATTENUATOR
APPLICATION INFORMATION
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS874003-02 provides
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. V
DD, VDDA, and VDDO should
be
individually
connected
to
the
power
supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance, power
supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA pin.
FIGURE 1. POWER SUPPLY FILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
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